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Searched refs:tf_shift (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
213 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
215 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
269 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
277 reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
296 reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
304 reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_degamma_reg_field()
469 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp1_program_input_csc()
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A Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
555 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument
565 dpp->tf_shift = tf_shift; in dpp1_construct()
A Ddcn10_dpp_dscl.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
410 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
A Ddcn10_resource.c420 static const struct dcn_dpp_shift tf_shift = { variable
652 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
A Ddcn10_dpp.h1356 const struct dcn_dpp_shift *tf_shift; member
1518 const struct dcn_dpp_shift *tf_shift,
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dpp_cm.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
179 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
181 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
184 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
188 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
193 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
195 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
197 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
201 reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
347 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
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A Ddcn30_dpp.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
643 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
647 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
652 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
654 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
656 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
660 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1484 const struct dcn3_dpp_shift *tf_shift, in dpp3_construct() argument
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A Ddcn30_dpp.h562 const struct dcn3_dpp_shift *tf_shift; member
581 const struct dcn3_dpp_shift *tf_shift,
A Ddcn30_resource.c554 static const struct dcn3_dpp_shift tf_shift = { variable
895 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn30_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp_cm.c47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
284 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
286 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
362 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
366 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
371 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
373 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
375 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
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A Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
419 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument
429 dpp->tf_shift = tf_shift; in dpp2_construct()
A Ddcn20_dpp.h682 const struct dcn2_dpp_shift *tf_shift; member
772 const struct dcn2_dpp_shift *tf_shift,
A Ddcn20_resource.c786 static const struct dcn2_dpp_shift tf_shift = { variable
1117 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_dpp.h61 const struct dcn201_dpp_shift *tf_shift; member
80 const struct dcn201_dpp_shift *tf_shift,
A Ddcn201_dpp.c42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
294 const struct dcn201_dpp_shift *tf_shift, in dpp201_construct() argument
304 dpp->tf_shift = tf_shift; in dpp201_construct()
A Ddcn201_resource.c475 static const struct dcn201_dpp_shift tf_shift = { variable
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c410 static const struct dcn3_dpp_shift tf_shift = { variable
737 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c664 static const struct dcn3_dpp_shift tf_shift = { variable
679 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c623 static const struct dcn3_dpp_shift tf_shift = { variable
638 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c667 static const struct dcn2_dpp_shift tf_shift = { variable
741 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c627 static const struct dcn3_dpp_shift tf_shift = { variable
1071 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()

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