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Searched refs:tile_width (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_fb.c197 unsigned int *tile_width, in intel_tile_block_dims() argument
508 tiles = *x / tile_width; in intel_compute_aligned_offset()
509 *x %= tile_width; in intel_compute_aligned_offset()
609 int tile_width, tile_height; in intel_fb_check_ccs_xy() local
624 tile_width *= hsub; in intel_fb_check_ccs_xy()
857 unsigned int tile_width = dims->tile_width; in calc_plane_remap_info() local
1159 u32 tile_width; in intel_fb_stride_alignment() local
1186 tile_width *= fb->pitches[0] <= tile_width * 8 ? 8 : 16; in intel_fb_stride_alignment()
1192 tile_width *= 4; in intel_fb_stride_alignment()
1204 tile_width *= 4; in intel_fb_stride_alignment()
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/linux/drivers/gpu/drm/i915/gem/
A Di915_gem_tiling.c121 unsigned int tile_width; in i915_tiling_ok() local
149 tile_width = 128; in i915_tiling_ok()
151 tile_width = 512; in i915_tiling_ok()
153 if (!stride || !IS_ALIGNED(stride, tile_width)) in i915_tiling_ok()
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_mdss.h376 u16 tile_width; member
/linux/drivers/media/platform/allegro-dvt/
A Dallegro-mail.h258 s32 tile_width[4]; member
A Dallegro-mail.c438 msg->tile_width[j] = src[i++]; in allegro_dec_encode_frame()
A Dallegro-core.c1894 pps->column_width_minus1[i] = msg->tile_width[i] - 1; in allegro_hevc_write_pps()
/linux/drivers/gpu/drm/radeon/
A Dr600_cs.c256 u32 tile_width = 8; in r600_get_array_mode_alignment() local
260 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; in r600_get_array_mode_alignment()
278 *pitch_align = max((u32)tile_width, in r600_get_array_mode_alignment()
286 *pitch_align = max((u32)macro_tile_width * tile_width, in r600_get_array_mode_alignment()
288 (values->blocksize * values->nsamples * tile_width))); in r600_get_array_mode_alignment()

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