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Searched refs:tiling (Results 1 – 25 of 36) sorted by relevance

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/linux/drivers/gpu/drm/i915/gem/
A Di915_gem_tiling.c60 if (tiling == I915_TILING_NONE) in i915_gem_fence_size()
66 stride *= i915_gem_tile_height(tiling); in i915_gem_fence_size()
94 unsigned int tiling, unsigned int stride) in i915_gem_fence_alignment() argument
102 if (tiling == I915_TILING_NONE) in i915_gem_fence_alignment()
118 unsigned int tiling, unsigned int stride) in i915_tiling_ok() argument
124 if (tiling == I915_TILING_NONE) in i915_tiling_ok()
127 if (tiling > I915_TILING_LAST) in i915_tiling_ok()
221 unsigned int tiling, unsigned int stride) in i915_gem_object_set_tiling() argument
271 if (tiling == I915_TILING_NONE) { in i915_gem_object_set_tiling()
289 vma->size, tiling, stride); in i915_gem_object_set_tiling()
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A Di915_gem_object.h335 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
337 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
338 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
355 unsigned int tiling, unsigned int stride);
/linux/drivers/gpu/drm/tegra/
A Dfb.c43 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
58 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
59 tiling->value = 0; in tegra_fb_get_tiling()
63 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
64 tiling->value = 0; in tegra_fb_get_tiling()
69 tiling->value = 0; in tegra_fb_get_tiling()
74 tiling->value = 1; in tegra_fb_get_tiling()
79 tiling->value = 2; in tegra_fb_get_tiling()
84 tiling->value = 3; in tegra_fb_get_tiling()
89 tiling->value = 4; in tegra_fb_get_tiling()
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A Dhub.c429 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
443 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_shared_plane_atomic_check()
447 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
453 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && in tegra_shared_plane_atomic_check()
634 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) in tegra_shared_plane_atomic_update()
708 unsigned long height = tegra_plane_state->tiling.value; in tegra_shared_plane_atomic_update()
711 switch (tegra_plane_state->tiling.mode) { in tegra_shared_plane_atomic_update()
A Dgem.h49 struct tegra_bo_tiling tiling; member
A Dplane.h49 struct tegra_bo_tiling tiling; member
A Dplane.c62 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
311 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
A Ddc.c418 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
420 switch (window->tiling.mode) { in tegra_dc_setup_window()
437 switch (window->tiling.mode) { in tegra_dc_setup_window()
617 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
649 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
653 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
749 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
A Ddrm.h187 struct tegra_bo_tiling *tiling);
A Ddrm.c639 bo->tiling.mode = mode; in tegra_gem_set_tiling()
640 bo->tiling.value = value; in tegra_gem_set_tiling()
661 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
674 args->value = bo->tiling.value; in tegra_gem_get_tiling()
/linux/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_client_blt.c33 enum client_tiling tiling; member
63 if (src->tiling == CLIENT_TILING_Y) in prepare_blit()
65 if (dst->tiling == CLIENT_TILING_Y) in prepare_blit()
82 if (src->tiling) { in prepare_blit()
88 if (dst->tiling) { in prepare_blit()
181 t->buffers[i].tiling = in tiled_blits_create_buffers()
207 enum client_tiling tiling) in tiled_offset() argument
217 if (tiling == CLIENT_TILING_X) { in tiled_offset()
256 switch (tiling) { in repr_tiling()
285 buf->tiling); in verify_buffer()
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A Di915_gem_mman.c25 unsigned int tiling; member
38 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
44 if (tile->tiling == I915_TILING_X) { in tiled_offset()
100 tile->tiling, tile->stride, err); in check_partial_mapping()
305 int tiling; in igt_partial_tiling() local
343 tile.tiling = I915_TILING_NONE; in igt_partial_tiling()
350 for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) { in igt_partial_tiling()
364 tile.tiling = tiling; in igt_partial_tiling()
365 switch (tiling) { in igt_partial_tiling()
475 tile.tiling = in igt_smoke_tiling()
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/linux/drivers/gpu/drm/i915/gt/
A Dintel_ggtt_fencing.c71 if (fence->tiling) { in i965_write_fence_reg()
80 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
112 if (fence->tiling) { in i915_write_fence_reg()
114 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
115 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
146 if (fence->tiling) { in i830_write_fence_reg()
150 if (fence->tiling == I915_TILING_Y) in i830_write_fence_reg()
203 fence->tiling = 0; in fence_update()
221 fence->tiling = i915_gem_object_get_tiling(vma->obj); in fence_update()
297 fence->tiling = 0; in i915_vma_revoke_fence()
A Dintel_ggtt_fencing.h40 u32 tiling; member
/linux/drivers/gpu/drm/i915/display/
A Dintel_plane_initial.c82 switch (plane_config->tiling) { in initial_plane_vma()
89 plane_config->tiling; in initial_plane_vma()
92 MISSING_CASE(plane_config->tiling); in initial_plane_vma()
234 if (plane_config->tiling) in intel_find_initial_plane_obj()
A Dintel_fb.c1330 unsigned int tiling, stride; in intel_framebuffer_init() local
1339 tiling = i915_gem_object_get_tiling(obj); in intel_framebuffer_init()
1348 if (tiling != I915_TILING_NONE && in intel_framebuffer_init()
1349 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
1355 if (tiling == I915_TILING_X) { in intel_framebuffer_init()
1357 } else if (tiling == I915_TILING_Y) { in intel_framebuffer_init()
1378 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { in intel_framebuffer_init()
1399 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { in intel_framebuffer_init()
A Dskl_universal_plane.c2250 u32 val, base, offset, stride_mult, tiling, alpha; in skl_get_initial_plane_config() local
2296 tiling = val & PLANE_CTL_TILED_MASK; in skl_get_initial_plane_config()
2297 switch (tiling) { in skl_get_initial_plane_config()
2302 plane_config->tiling = I915_TILING_X; in skl_get_initial_plane_config()
2306 plane_config->tiling = I915_TILING_Y; in skl_get_initial_plane_config()
2323 MISSING_CASE(tiling); in skl_get_initial_plane_config()
/linux/drivers/gpu/drm/vc4/
A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
A Dvc4_plane.c642 u32 tiling, src_y; in vc4_plane_mode_set() local
680 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
743 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
776 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
780 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
784 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
839 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
889 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
/linux/drivers/staging/media/ipu3/
A Dipu3-css-params.c313 unsigned int tiling; member
426 unsigned int tiling = 0; in imgu_css_osys_calc_frame_and_stripe_params() local
466 &tiling); in imgu_css_osys_calc_frame_and_stripe_params()
472 frame_params[pin].tiling = tiling; in imgu_css_osys_calc_frame_and_stripe_params()
1001 fr_pr->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
1084 if (frame_params[pin].tiling) { in imgu_css_osys_calc()
1153 param->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
A Ddisplay_rq_dlg_calc_20v2.c343 unsigned int tiling, in get_meta_and_pte_attr() argument
348 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
419 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
457 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c330 unsigned int tiling, in get_meta_and_pte_attr() argument
336 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
411 (enum dm_swizzle_mode) (tiling), in get_meta_and_pte_attr()
449 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c377 unsigned int tiling, in get_meta_and_pte_attr() argument
384 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
454 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
494 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c396 unsigned int tiling, in get_meta_and_pte_attr() argument
403 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
472 (enum dm_swizzle_mode) (tiling), in get_meta_and_pte_attr()
511 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()

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