| /linux/Documentation/devicetree/bindings/arm/mediatek/ |
| A D | mediatek,topckgen.txt | 1 Mediatek topckgen controller
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6765-topckgen", "syscon"
13 - "mediatek,mt6797-topckgen"
14 - "mediatek,mt7622-topckgen"
15 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
16 - "mediatek,mt7629-topckgen"
17 - "mediatek,mt8135-topckgen"
19 - "mediatek,mt8173-topckgen"
[all …]
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| A D | mediatek,mt8195-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
28 - mediatek,mt8195-topckgen
48 topckgen: syscon@10000000 {
49 compatible = "mediatek,mt8195-topckgen", "syscon";
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| A D | mediatek,mt8192-sys-clock.yaml | 20 - mediatek,mt8192-topckgen
40 topckgen: syscon@10000000 {
41 compatible = "mediatek,mt8192-topckgen", "syscon";
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8516.dtsi | 182 topckgen: topckgen@10000000 { label
219 <&topckgen CLK_TOP_APXGPT>;
306 <&topckgen CLK_TOP_UART0>;
320 <&topckgen CLK_TOP_UART1>;
334 <&topckgen CLK_TOP_UART2>;
350 <&topckgen CLK_TOP_I2C0>,
351 <&topckgen CLK_TOP_APDMA>;
369 <&topckgen CLK_TOP_I2C1>,
370 <&topckgen CLK_TOP_APDMA>;
388 <&topckgen CLK_TOP_I2C2>,
[all …]
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| A D | mt7622.dtsi | 252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
325 clocks = <&topckgen CLK_TOP_RTC>;
492 <&topckgen CLK_TOP_SPI0_SEL>,
562 <&topckgen CLK_TOP_FLASH_SEL>;
574 <&topckgen CLK_TOP_SPI1_SEL>,
605 <&topckgen CLK_TOP_AUD1_SEL>,
606 <&topckgen CLK_TOP_AUD2_SEL>,
677 <&topckgen CLK_TOP_AUD2PLL>;
699 <&topckgen CLK_TOP_AXI_SEL>;
[all …]
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| A D | mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
290 <&topckgen CLK_TOP_VDEC_SEL>;
555 <&topckgen CLK_TOP_SPI_SEL>,
634 <&topckgen CLK_TOP_SPI_SEL>,
647 <&topckgen CLK_TOP_SPI_SEL>,
[all …]
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| A D | mt8183.dtsi | 370 topckgen: syscon@10000000 { label
539 <&topckgen CLK_TOP_MUX_DSP>,
740 <&topckgen CLK_TOP_MUX_SPI>,
928 <&topckgen CLK_TOP_MUX_SPI>,
955 <&topckgen CLK_TOP_MUX_SPI>,
968 <&topckgen CLK_TOP_MUX_SPI>,
1041 <&topckgen CLK_TOP_MUX_SPI>,
1054 <&topckgen CLK_TOP_MUX_SPI>,
1150 <&topckgen CLK_TOP_APLL1_CK>,
1152 <&topckgen CLK_TOP_APLL2_CK>,
[all …]
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| A D | mt8173.dtsi | 475 <&topckgen CLK_TOP_VENC_SEL>;
761 <&topckgen CLK_TOP_SPI_SEL>,
854 <&topckgen CLK_TOP_AUDIO_SEL>,
856 <&topckgen CLK_TOP_APLL1_DIV0>,
857 <&topckgen CLK_TOP_APLL2_DIV0>,
858 <&topckgen CLK_TOP_I2S0_M_SEL>,
876 <&topckgen CLK_TOP_APLL2>;
894 <&topckgen CLK_TOP_AXI_SEL>;
904 <&topckgen CLK_TOP_AXI_SEL>;
1405 <&topckgen CLK_TOP_VDEC_SEL>,
[all …]
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| A D | mt8167.dtsi | 20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
52 clocks = <&topckgen CLK_TOP_SMI_MM>;
60 clocks = <&topckgen CLK_TOP_SMI_MM>,
61 <&topckgen CLK_TOP_RG_VDEC>;
68 clocks = <&topckgen CLK_TOP_SMI_MM>;
75 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
76 <&topckgen CLK_TOP_RG_SLOW_MFG>;
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| A D | mt6797.dtsi | 114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
81 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
82 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
83 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
[all …]
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| A D | mt8195-afe-pcm.yaml | 22 mediatek,topckgen:
124 - mediatek,topckgen
140 mediatek,topckgen = <&topckgen>;
143 <&topckgen 163>, //CLK_TOP_APLL1
144 <&topckgen 166>, //CLK_TOP_APLL2
152 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL
154 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL
155 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL
156 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL
157 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL
[all …]
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| A D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
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| A D | mt6797-afe-pcm.txt | 29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
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| A D | mt8192-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
64 - mediatek,topckgen
86 mediatek,topckgen = <&topckgen>;
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| A D | mt8183-afe-pcm.txt | 32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
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| /linux/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
138 topckgen: syscon@10210000 { label
254 <&topckgen CLK_TOP_UNIVPLL2_D4>;
283 <&topckgen CLK_TOP_SPI0_SEL>,
294 <&topckgen CLK_TOP_FLASH_SEL>;
321 <&topckgen CLK_TOP_SATA_SEL>,
322 <&topckgen CLK_TOP_HIF_SEL>;
389 <&topckgen CLK_TOP_AXI_SEL>,
390 <&topckgen CLK_TOP_HIF_SEL>;
392 <&topckgen CLK_TOP_SYSPLL1_D2>,
[all …]
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| A D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
404 <&topckgen CLK_TOP_SPI1_SEL>,
417 <&topckgen CLK_TOP_SPI2_SEL>,
436 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
616 <&topckgen CLK_TOP_ETHIF_SEL>;
[all …]
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| A D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
568 <&topckgen CLK_TOP_SPI1_SEL>,
582 <&topckgen CLK_TOP_SPI2_SEL>,
867 <&topckgen CLK_TOP_ETHIF_SEL>;
[all …]
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | mediatek-vcodec.txt | 63 <&topckgen CLK_TOP_UNIVPLL_D2>,
64 <&topckgen CLK_TOP_CCI400_SEL>,
65 <&topckgen CLK_TOP_VDEC_SEL>,
66 <&topckgen CLK_TOP_VCODECPLL>,
68 <&topckgen CLK_TOP_VENC_LT_SEL>,
69 <&topckgen CLK_TOP_VCODECPLL_370P5>;
79 <&topckgen CLK_TOP_CCI400_SEL>,
80 <&topckgen CLK_TOP_VDEC_SEL>,
106 clocks = <&topckgen CLK_TOP_VENC_SEL>;
108 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
[all …]
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| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-slave-mt27xx.txt | 14 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
17 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
21 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
31 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
32 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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| A D | spi-mt65xx.txt | 31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
33 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
35 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
36 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
62 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
63 <&topckgen CLK_TOP_SPI_SEL>,
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| /linux/Documentation/devicetree/bindings/net/ |
| A D | mediatek-dwmac.txt | 71 <&topckgen CLK_TOP_ETHER_125M_SEL>,
72 <&topckgen CLK_TOP_ETHER_50M_SEL>,
73 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
74 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
75 <&topckgen CLK_TOP_ETHER_50M_SEL>,
76 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
77 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
78 <&topckgen CLK_TOP_APLL1_D3>,
79 <&topckgen CLK_TOP_ETHERPLL_50M>;
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| A D | mediatek,star-emac.yaml | 76 clocks = <&topckgen CLK_TOP_RG_ETH>,
77 <&topckgen CLK_TOP_66M_ETH>,
78 <&topckgen CLK_TOP_133M_ETH>;
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| /linux/Documentation/devicetree/bindings/power/ |
| A D | mediatek,power-controller.yaml | 242 clocks = <&topckgen CLK_TOP_MM_SEL>;
248 clocks = <&topckgen CLK_TOP_MM_SEL>,
249 <&topckgen CLK_TOP_VENC_SEL>;
255 clocks = <&topckgen CLK_TOP_MM_SEL>;
261 clocks = <&topckgen CLK_TOP_MM_SEL>;
268 clocks = <&topckgen CLK_TOP_MM_SEL>,
269 <&topckgen CLK_TOP_VENC_LT_SEL>;
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