Searched refs:triggered_crtc_reset (Results 1 – 5 of 5) sorted by relevance
229 struct crtc_trigger_info triggered_crtc_reset; member
6001 if (stream->triggered_crtc_reset.enabled) { in set_multisync_trigger_params()6002 master = stream->triggered_crtc_reset.event_source; in set_multisync_trigger_params()6003 stream->triggered_crtc_reset.event = in set_multisync_trigger_params()6006 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; in set_multisync_trigger_params()6016 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { in set_master_stream()6029 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; in set_master_stream()10138 new_stream->triggered_crtc_reset.enabled = in dm_update_crtc_state()11443 ->triggered_crtc_reset.enabled = in amdgpu_dm_trigger_timing_sync()
1324 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) in enable_timing_multisync()1326 …if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event… in enable_timing_multisync()
2623 &grouped_pipes[i]->stream->triggered_crtc_reset);
2265 &grouped_pipes[i]->stream->triggered_crtc_reset); in dcn10_enable_per_frame_crtc_position_reset()
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