| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 337 ttu_regs->qos_level_low_wm); in print__ttu_regs_st()
340 ttu_regs->qos_level_high_wm); in print__ttu_regs_st()
343 ttu_regs->min_ttu_vblank); in print__ttu_regs_st()
346 ttu_regs->qos_level_flip); in print__ttu_regs_st()
373 ttu_regs->qos_level_fixed_l); in print__ttu_regs_st()
376 ttu_regs->qos_ramp_disable_l); in print__ttu_regs_st()
379 ttu_regs->qos_level_fixed_c); in print__ttu_regs_st()
382 ttu_regs->qos_ramp_disable_c); in print__ttu_regs_st()
385 ttu_regs->qos_level_fixed_cur0); in print__ttu_regs_st()
388 ttu_regs->qos_ramp_disable_cur0); in print__ttu_regs_st()
[all …]
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| A D | dml1_display_rq_dlg_calc.h | 57 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_helpers.h | 44 …tu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
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| A D | display_mode_lib.h | 52 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 304 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr; in dcn10_get_ttu_states() local
311 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_get_ttu_states()
312 …ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delive… in dcn10_get_ttu_states()
313 …ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per… in dcn10_get_ttu_states()
314 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1, in dcn10_get_ttu_states()
315 …ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disabl… in dcn10_get_ttu_states()
316 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_get_ttu_states()
317 … ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1); in dcn10_get_ttu_states()
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| A D | dcn10_hw_sequencer.c | 262 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr; in dcn10_log_hubp_states() local
266 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_log_hubp_states()
267 …ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delive… in dcn10_log_hubp_states()
268 …ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per… in dcn10_log_hubp_states()
269 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1, in dcn10_log_hubp_states()
270 …ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disabl… in dcn10_log_hubp_states()
271 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_log_hubp_states()
272 … ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1); in dcn10_log_hubp_states()
2683 &pipe_ctx->ttu_regs, in dcn10_update_dchubp_dpp()
2689 &pipe_ctx->ttu_regs); in dcn10_update_dchubp_dpp()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | hubp.h | 93 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
100 struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
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| A D | mem_input.h | 97 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.h | 63 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_20v2.h | 63 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_20.c | 1551 display_ttu_regs_st *ttu_regs, in dml20_rq_dlg_get_dlg_reg() argument
1593 ttu_regs, in dml20_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_20v2.c | 1552 display_ttu_regs_st *ttu_regs, in dml20v2_rq_dlg_get_dlg_reg() argument
1594 ttu_regs, in dml20v2_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.h | 59 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_30.c | 1833 display_ttu_regs_st *ttu_regs, in dml30_rq_dlg_get_dlg_reg() argument
1875 ttu_regs, in dml30_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.h | 59 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_31.c | 1679 display_ttu_regs_st *ttu_regs, in dml31_rq_dlg_get_dlg_reg() argument
1714 ttu_regs, in dml31_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.h | 63 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_21.c | 1660 display_ttu_regs_st *ttu_regs, in dml21_rq_dlg_get_dlg_reg() argument
1706 ttu_regs, in dml21_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 378 struct _vcs_dpi_display_ttu_regs_st ttu_regs; member
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| /linux/drivers/gpu/drm/amd/display/dc/calcs/ |
| A D | dcn_calcs.c | 460 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs; in dcn_bw_calc_rq_dlg_ttu() local
471 memset(ttu_regs, 0, sizeof(*ttu_regs)); in dcn_bw_calc_rq_dlg_ttu()
513 ttu_regs, in dcn_bw_calc_rq_dlg_ttu()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hwseq.c | 1351 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; in dcn20_detect_pipe_changes()
1353 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; in dcn20_detect_pipe_changes()
1396 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || in dcn20_detect_pipe_changes()
1426 &pipe_ctx->ttu_regs, in dcn20_update_dchubp_dpp()
1437 &pipe_ctx->ttu_regs); in dcn20_update_dchubp_dpp()
1898 &pipe_ctx->ttu_regs, in dcn20_update_bandwidth()
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| A D | dcn20_resource.c | 3175 &context->res_ctx.pipe_ctx[i].ttu_regs, in dcn20_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 2868 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; in commit_planes_for_stream()
2990 &context->res_ctx.pipe_ctx[i].ttu_regs); in commit_planes_for_stream()
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