1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */ 3 4 /* Written 1995 by Werner Almesberger, EPFL LRC */ 5 6 7 #ifndef DRIVERS_ATM_uPD98401_H 8 #define DRIVERS_ATM_uPD98401_H 9 10 11 #define MAX_CRAM_SIZE (1 << 18) /* 2^18 words */ 12 #define RAM_INCREMENT 1024 /* check in 4 kB increments */ 13 14 #define uPD98401_PORTS 0x24 /* probably more ? */ 15 16 17 /* 18 * Commands 19 */ 20 21 #define uPD98401_OPEN_CHAN 0x20000000 /* open channel */ 22 #define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */ 23 #define uPD98401_CHAN_ADDR_SHIFT 3 24 #define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */ 25 #define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */ 26 #define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */ 27 #define uPD98401_TX_READY 0x30000000 /* TX ready */ 28 #define uPD98401_ADD_BAT 0x34000000 /* add batches */ 29 #define uPD98401_POOL 0x000f0000 /* pool number */ 30 #define uPD98401_POOL_SHIFT 16 31 #define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */ 32 #define uPD98401_NOP 0x3f000000 /* NOP */ 33 #define uPD98401_IND_ACC 0x00000000 /* Indirect Access */ 34 #define uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */ 35 #define uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */ 36 #define uPD98401_IA_B2 0x04000000 37 #define uPD98401_IA_B1 0x02000000 38 #define uPD98401_IA_B0 0x01000000 39 #define uPD98401_IA_BALL 0x0f000000 /* whole longword */ 40 #define uPD98401_IA_TGT 0x000c0000 /* Target */ 41 #define uPD98401_IA_TGT_SHIFT 18 42 #define uPD98401_IA_TGT_CM 0 /* - Control Memory */ 43 #define uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */ 44 #define uPD98401_IA_TGT_PHY 3 /* - PHY device */ 45 #define uPD98401_IA_ADDR 0x0003ffff 46 47 /* 48 * Command Register Status 49 */ 50 51 #define uPD98401_BUSY 0x80000000 /* SAR is busy */ 52 #define uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */ 53 54 /* 55 * Indications 56 */ 57 58 /* Normal (AAL5) Receive Indication */ 59 #define uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */ 60 #define uPD98401_AAL5_UINFO_SHIFT 16 61 #define uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */ 62 #define uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */ 63 #define uPD98401_AAL5_CHAN_SHIFT 16 64 #define uPD98401_AAL5_ERR 0x00008000 /* Error indication */ 65 #define uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */ 66 #define uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */ 67 #define uPD98401_AAL5_ES 0x00000f00 /* Error Status */ 68 #define uPD98401_AAL5_ES_SHIFT 8 69 #define uPD98401_AAL5_ES_NONE 0 /* No error */ 70 #define uPD98401_AAL5_ES_FREE 1 /* Receiver free buf underflow */ 71 #define uPD98401_AAL5_ES_FIFO 2 /* Receiver FIFO overrun */ 72 #define uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */ 73 #define uPD98401_AAL5_ES_CRC 4 /* CRC error */ 74 #define uPD98401_AAL5_ES_ABORT 5 /* User abort */ 75 #define uPD98401_AAL5_ES_LENGTH 6 /* Length violation */ 76 #define uPD98401_AAL5_ES_T1 7 /* T1 error (timeout) */ 77 #define uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */ 78 #define uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */ 79 80 /* Raw Cell Indication */ 81 #define uPD98401_RAW_UINFO uPD98401_AAL5_UINFO 82 #define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT 83 #define uPD98401_RAW_HEC 0x000000ff /* HEC */ 84 #define uPD98401_RAW_CHAN uPD98401_AAL5_CHAN 85 #define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT 86 87 /* Transmit Indication */ 88 #define uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */ 89 #define uPD98401_TXI_CONN_SHIFT 16 90 #define uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */ 91 #define uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */ 92 93 /* 94 * Directly Addressable Registers 95 */ 96 97 #define uPD98401_GMR 0x00 /* General Mode Register */ 98 #define uPD98401_GSR 0x01 /* General Status Register */ 99 #define uPD98401_IMR 0x02 /* Interrupt Mask Register */ 100 #define uPD98401_RQU 0x03 /* Receive Queue Underrun */ 101 #define uPD98401_RQA 0x04 /* Receive Queue Alert */ 102 #define uPD98401_ADDR 0x05 /* Last Burst Address */ 103 #define uPD98401_VER 0x06 /* Version Number */ 104 #define uPD98401_SWR 0x07 /* Software Reset */ 105 #define uPD98401_CMR 0x08 /* Command Register */ 106 #define uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */ 107 #define uPD98401_CER 0x0a /* Command Extension Register */ 108 #define uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */ 109 110 #define uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */ 111 #define uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */ 112 #define uPD98401_MBA(n) (0x18+(n)) /* Mailbox n Bottom Address */ 113 #define uPD98401_MTA(n) (0x1c+(n)) /* Mailbox n Tail Address */ 114 #define uPD98401_MWA(n) (0x20+(n)) /* Mailbox n Write Address */ 115 116 /* GMR is at 0x00 */ 117 #define uPD98401_GMR_ONE 0x80000000 /* Must be set to one */ 118 #define uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */ 119 #define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */ 120 #define uPD98401_GMR_LP 0x00004000 /* Loopback */ 121 #define uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */ 122 #define uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */ 123 #define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */ 124 #define uPD98401_BURST16 0x00000800 /* 16-word burst */ 125 #define uPD98401_BURST8 0x00000400 /* 8-word burst */ 126 #define uPD98401_BURST4 0x00000200 /* 4-word burst */ 127 #define uPD98401_BURST2 0x00000100 /* 2-word burst */ 128 #define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */ 129 #define uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */ 130 #define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/ 131 #define uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */ 132 #define uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */ 133 #define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/ 134 #define uPD98401_GMR_SE 0x00000002 /* Shapers Enable */ 135 #define uPD98401_GMR_RE 0x00000001 /* Receiver Enable */ 136 137 /* GSR is at 0x01, IMR is at 0x02 */ 138 #define uPD98401_INT_PI 0x80000000 /* PHY interrupt */ 139 #define uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */ 140 #define uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */ 141 #define uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */ 142 #define uPD98401_INT_SPE 0x08000000 /* System Parity Error */ 143 #define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */ 144 #define uPD98401_INT_SBE 0x02000000 /* System Bus Error */ 145 #define uPD98401_INT_IND 0x01000000 /* Initialization Done */ 146 #define uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */ 147 #define uPD98401_INT_RCR_SHIFT 8 148 #define uPD98401_INT_MF 0x000000f0 /* Mailbox Full */ 149 #define uPD98401_INT_MF_SHIFT 4 150 #define uPD98401_INT_MM 0x0000000f /* Mailbox Modified */ 151 152 /* VER is at 0x06 */ 153 #define uPD98401_MAJOR 0x0000ff00 /* Major revision */ 154 #define uPD98401_MAJOR_SHIFT 8 155 #define uPD98401_MINOR 0x000000ff /* Minor revision */ 156 157 /* 158 * Indirectly Addressable Registers 159 */ 160 161 #define uPD98401_IM(n) (0x40000+(n)) /* Scheduler n I and M */ 162 #define uPD98401_X(n) (0x40010+(n)) /* Scheduler n X */ 163 #define uPD98401_Y(n) (0x40020+(n)) /* Scheduler n Y */ 164 #define uPD98401_PC(n) (0x40030+(n)) /* Scheduler n P, C, p and c */ 165 #define uPD98401_PS(n) (0x40040+(n)) /* Scheduler n priority and status */ 166 167 /* IM contents */ 168 #define uPD98401_IM_I 0xff000000 /* I */ 169 #define uPD98401_IM_I_SHIFT 24 170 #define uPD98401_IM_M 0x00ffffff /* M */ 171 172 /* PC contents */ 173 #define uPD98401_PC_P 0xff000000 /* P */ 174 #define uPD98401_PC_P_SHIFT 24 175 #define uPD98401_PC_C 0x00ff0000 /* C */ 176 #define uPD98401_PC_C_SHIFT 16 177 #define uPD98401_PC_p 0x0000ff00 /* p */ 178 #define uPD98401_PC_p_SHIFT 8 179 #define uPD98401_PC_c 0x000000ff /* c */ 180 181 /* PS contents */ 182 #define uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */ 183 #define uPD98401_PS_PRIO_SHIFT 4 184 #define uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */ 185 #define uPD98401_PS_R 0x04 /* Round Robin (internal) */ 186 #define uPD98401_PS_A 0x02 /* Active (internal) */ 187 #define uPD98401_PS_E 0x01 /* Enabled */ 188 189 #define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */ 190 #define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */ 191 #define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */ 192 #define uPD98401_T1R 0x40300 /* T1 Register */ 193 #define uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */ 194 #define uPD98401_TSR 0x40302 /* Time-Stamp Register */ 195 196 /* VRR is at 0x40301 */ 197 #define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */ 198 #define uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */ 199 #define uPD98401_VRR_SHIFT_SHIFT 16 200 #define uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */ 201 202 /* 203 * TX packet descriptor 204 */ 205 206 #define uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */ 207 208 #define uPD98401_TXPD_V 0x80000000 /* Valid bit */ 209 #define uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */ 210 #define uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */ 211 #define uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */ 212 #define uPD98401_CLPM_0 0 /* 00 CLP = 0 */ 213 #define uPD98401_CLPM_1 3 /* 11 CLP = 1 */ 214 #define uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */ 215 #define uPD98401_TXPD_CLPM_SHIFT 27 216 #define uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */ 217 #define uPD98401_TXPD_PTI_SHIFT 24 218 #define uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */ 219 #define uPD98401_TXPD_GFC_SHIFT 20 220 #define uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */ 221 #define uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */ 222 #define uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */ 223 #define uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */ 224 #define uPD98401_TXPD_UU_SHIFT 8 225 #define uPD98401_TXPD_CPI 0x000000ff /* CPI */ 226 227 /* 228 * TX buffer descriptor 229 */ 230 231 #define uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */ 232 233 #define uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */ 234 235 /* 236 * TX VC table 237 */ 238 239 /* 1st word has the same structure as in a TX packet descriptor */ 240 #define uPD98401_TXVC_L 0x80000000 /* last buffer */ 241 #define uPD98401_TXVC_SHP 0x0f000000 /* shaper number */ 242 #define uPD98401_TXVC_SHP_SHIFT 24 243 #define uPD98401_TXVC_VPI 0x00ff0000 /* VPI */ 244 #define uPD98401_TXVC_VPI_SHIFT 16 245 #define uPD98401_TXVC_VCI 0x0000ffff /* VCI */ 246 #define uPD98401_TXVC_QRP 6 /* Queue Read Pointer is in word 6 */ 247 248 /* 249 * RX free buffer pools descriptor 250 */ 251 252 #define uPD98401_RXFP_ALERT 0x70000000 /* low water mark */ 253 #define uPD98401_RXFP_ALERT_SHIFT 28 254 #define uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */ 255 #define uPD98401_RXFP_BFSZ_SHIFT 24 256 #define uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */ 257 #define uPD98401_RXFP_BTSZ_SHIFT 16 258 #define uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */ 259 260 /* 261 * RX VC table 262 */ 263 264 #define uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */ 265 #define uPD98401_RXVC_BTSZ_SHIFT 24 266 #define uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */ 267 #define uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */ 268 #define uPD98401_RXVC_POOL_SHIFT 16 269 #define uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */ 270 #define uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */ 271 #define uPD98401_RXVC_T1_SHIFT 16 272 #define uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */ 273 #define uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */ 274 #define uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */ 275 #define uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */ 276 #define uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */ 277 #define uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */ 278 #define uPD98401_RXVC_REM_SHIFT 17 279 #define uPD98401_RXVC_CLP 0x00010000 /* CLP received */ 280 #define uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */ 281 #define uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */ 282 #define uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */ 283 #define uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */ 284 #define uPD98401_RXVC_DP 0x00000800 /* like PR ? */ 285 #define uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */ 286 287 /* 288 * RX lookup table 289 */ 290 291 #define uPD98401_RXLT_ENBL 0x8000 /* Enable */ 292 293 #endif 294