/linux/drivers/gpu/drm/amd/amdkfd/ |
A D | kfd_packet_manager_v9.c | 66 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v9() 71 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v9() 105 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran() 110 upper_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran() 148 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v9() 173 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_v9() 176 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9() 237 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_v9() 243 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9() 342 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_v9() [all …]
|
A D | kfd_packet_manager_vi.c | 69 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_vi() 108 packet->bitfields3.ib_base_hi = upper_32_bits(ib); in pm_runlist_vi() 133 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_vi() 136 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi() 188 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_vi() 194 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi() 282 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_vi() 284 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_vi() 312 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_vi()
|
A D | kfd_mqd_manager_vi.c | 117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd() 131 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); in init_mqd() 133 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); in init_mqd() 144 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd() 185 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd() 188 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd() 190 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd() 217 upper_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd() 369 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma() 371 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
|
A D | kfd_mqd_manager_v10.c | 113 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd() 130 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd() 179 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd() 182 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd() 184 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd() 206 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd() 344 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma() 346 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
|
A D | kfd_mqd_manager_v9.c | 160 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd() 182 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd() 228 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd() 231 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd() 233 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd() 257 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd() 399 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma() 401 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
|
/linux/drivers/gpu/drm/radeon/ |
A D | si_dma.c | 82 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages() 83 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages() 121 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages() 133 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages() 173 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages() 177 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages() 265 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma() 266 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
|
A D | ni_dma.c | 134 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute() 145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute() 222 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume() 330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages() 331 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages() 370 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages() 382 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages() 422 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages() 426 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
|
A D | r600_dma.c | 143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume() 255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test() 295 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit() 322 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit() 360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test() 415 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute() 426 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute() 478 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma() 479 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
|
A D | evergreen_dma.c | 48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit() 78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute() 89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute() 142 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma() 143 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
|
A D | cik_sdma.c | 155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute() 208 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit() 237 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit() 670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test() 728 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test() 817 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages() 819 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pages() 858 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pages() 871 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cik_sdma_vm_write_pages() 911 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_set_pages() [all …]
|
/linux/drivers/gpu/drm/amd/amdgpu/ |
A D | si_dma.c | 100 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence() 107 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence() 108 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence() 279 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib() 327 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte() 328 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte() 350 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte() 353 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pte() 391 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pte_pde() 393 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in si_dma_vm_set_pte_pde() [all …]
|
A D | sdma_v2_4.c | 319 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence() 327 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence() 328 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v2_4_ring_emit_fence() 573 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring() 628 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib() 682 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v2_4_vm_copy_pte() 684 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_copy_pte() 707 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_write_pte() 735 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_set_pte_pde() 737 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v2_4_vm_set_pte_pde() [all …]
|
A D | sdma_v5_2.c | 294 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr() 308 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr() 312 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr() 442 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence() 453 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence() 454 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_2_ring_emit_fence() 637 upper_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume() 993 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib() 1052 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_copy_pte() 1076 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_write_pte() [all …]
|
A D | cik_sdma.c | 287 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence() 295 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence() 296 amdgpu_ring_write(ring, upper_32_bits(seq)); in cik_sdma_ring_emit_fence() 638 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring() 693 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib() 743 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pte() 745 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pte() 768 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pte() 796 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_set_pte_pde() 798 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in cik_sdma_vm_set_pte_pde() [all …]
|
A D | sdma_v5_0.c | 407 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr() 421 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr() 425 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr() 557 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence() 569 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_0_ring_emit_fence() 756 upper_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume() 787 upper_32_bits(ring->wptr) << 2); in sdma_v5_0_gfx_resume() 1072 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_0_ring_test_ib() 1131 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_copy_pte() 1155 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_write_pte() [all …]
|
A D | sdma_v3_0.c | 493 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence() 501 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence() 502 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v3_0_ring_emit_fence() 723 upper_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume() 900 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib() 953 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v3_0_vm_copy_pte() 955 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v3_0_vm_copy_pte() 978 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v3_0_vm_write_pte() 1006 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v3_0_vm_set_pte_pde() 1008 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v3_0_vm_set_pte_pde() [all …]
|
A D | vcn_v2_0.c | 341 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume() 353 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume() 369 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); in vcn_v2_0_mc_resume() 898 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode() 904 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode() 1064 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start() 1618 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v2_0_enc_ring_emit_fence() 1896 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov() 1930 upper_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov() 1947 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov() [all …]
|
/linux/drivers/pci/controller/mobiveil/ |
A D | pcie-mobiveil.c | 154 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ib_windows() 159 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ib_windows() 164 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ib_windows() 195 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ob_windows() 205 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ob_windows() 210 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ob_windows()
|
/linux/drivers/pci/controller/ |
A D | pci-xgene.c | 300 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); in xgene_pcie_set_ib_mask() 304 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask() 390 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg() 392 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); in xgene_pcie_setup_ob_reg() 394 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg() 402 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); in xgene_pcie_setup_cfg_reg() 452 upper_32_bits(pim) | EN_COHERENCY); in xgene_pcie_setup_pims() 454 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); in xgene_pcie_setup_pims() 512 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); in xgene_pcie_setup_ib_reg() 522 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ib_reg() [all …]
|
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
A D | gm20b.c | 84 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch() 87 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch() 90 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch() 114 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write() 115 .data_dma_base1 = upper_32_bits(data), in gm20b_pmu_acr_bld_write() 116 .overlay_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
|
/linux/arch/x86/include/asm/ |
A D | mshyperv.h | 57 u32 input_address_hi = upper_32_bits(input_address); in hv_do_hypercall() 59 u32 output_address_hi = upper_32_bits(output_address); in hv_do_hypercall() 92 u32 input1_hi = upper_32_bits(input1); in hv_do_fast_hypercall8() 125 u32 input1_hi = upper_32_bits(input1); in hv_do_fast_hypercall16() 127 u32 input2_hi = upper_32_bits(input2); in hv_do_fast_hypercall16()
|
/linux/drivers/net/ethernet/apm/xgene-v2/ |
A D | ring.c | 28 dma_h = upper_32_bits(next_dma); in xge_setup_desc() 40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr() 52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
|
/linux/drivers/media/pci/pt3/ |
A D | pt3_dma.c | 54 iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma() 185 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf() 191 d->addr_h = upper_32_bits(data_addr); in pt3_alloc_dmabuf() 196 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf() 205 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
|
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
A D | gm20b.c | 42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch() 45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch() 66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write() 67 .data_dma_base1 = upper_32_bits(data), in gm20b_gr_acr_bld_write()
|
/linux/drivers/pci/controller/dwc/ |
A D | pcie-designware.c | 280 upper_32_bits(cpu_addr)); in dw_pcie_prog_outbound_atu_unroll() 284 upper_32_bits(limit_addr)); in dw_pcie_prog_outbound_atu_unroll() 288 upper_32_bits(pci_addr)); in dw_pcie_prog_outbound_atu_unroll() 290 val = upper_32_bits(size - 1) ? in dw_pcie_prog_outbound_atu_unroll() 333 upper_32_bits(cpu_addr)); in __dw_pcie_prog_outbound_atu() 338 upper_32_bits(cpu_addr + size - 1)); in __dw_pcie_prog_outbound_atu() 342 upper_32_bits(pci_addr)); in __dw_pcie_prog_outbound_atu() 344 val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ? in __dw_pcie_prog_outbound_atu() 405 upper_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu_unroll() 456 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
|