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Searched refs:v (Results 1 – 25 of 1932) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calc_auto.c67 v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor; in scaler_settings_calculation()
68 v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor; in scaler_settings_calculation()
132 …v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps… in mode_support_and_system_configuration()
340 …v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(… in mode_support_and_system_configuration()
747 …v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) /… in mode_support_and_system_configuration()
802 …v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel… in mode_support_and_system_configuration()
1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1393 v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 …v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispcl… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all …]
/linux/include/linux/atomic/
A Datomic-instrumented.h27 instrument_atomic_read(v, sizeof(*v)); in atomic_read()
34 instrument_atomic_read(v, sizeof(*v)); in atomic_read_acquire()
41 instrument_atomic_write(v, sizeof(*v)); in atomic_set()
48 instrument_atomic_write(v, sizeof(*v)); in atomic_set_release()
55 instrument_atomic_read_write(v, sizeof(*v)); in atomic_add()
62 instrument_atomic_read_write(v, sizeof(*v)); in atomic_add_return()
69 instrument_atomic_read_write(v, sizeof(*v)); in atomic_add_return_acquire()
76 instrument_atomic_read_write(v, sizeof(*v)); in atomic_add_return_release()
83 instrument_atomic_read_write(v, sizeof(*v)); in atomic_add_return_relaxed()
605 instrument_atomic_read(v, sizeof(*v)); in atomic64_read()
[all …]
A Datomic-long.h41 arch_atomic64_set(v, i); in arch_atomic_long_set()
53 arch_atomic64_add(i, v); in arch_atomic_long_add()
107 arch_atomic64_sub(i, v); in arch_atomic_long_sub()
161 arch_atomic64_inc(v); in arch_atomic_long_inc()
215 arch_atomic64_dec(v); in arch_atomic_long_dec()
535 arch_atomic_set(v, i); in arch_atomic_long_set()
547 arch_atomic_add(i, v); in arch_atomic_long_add()
601 arch_atomic_sub(i, v); in arch_atomic_long_sub()
655 arch_atomic_inc(v); in arch_atomic_long_inc()
709 arch_atomic_dec(v); in arch_atomic_long_dec()
[all …]
A Datomic-arch-fallback.h338 arch_atomic_inc(atomic_t *v) in arch_atomic_inc() argument
340 arch_atomic_add(1, v); in arch_atomic_inc()
509 arch_atomic_dec(atomic_t *v) in arch_atomic_dec() argument
511 arch_atomic_sub(1, v); in arch_atomic_dec()
724 arch_atomic_and(~i, v); in arch_atomic_andnot()
1158 int c = arch_atomic_read(v); in arch_atomic_fetch_add_unless()
1208 int c = arch_atomic_read(v); in arch_atomic_inc_unless_negative()
1224 int c = arch_atomic_read(v); in arch_atomic_dec_unless_positive()
1447 arch_atomic64_add(1, v); in arch_atomic64_inc()
1618 arch_atomic64_sub(1, v); in arch_atomic64_dec()
[all …]
/linux/drivers/media/platform/
A Dimx-pxp.h219 #define BF_PXP_OUT_BUF_ADDR(v) (v) argument
225 #define BF_PXP_OUT_BUF2_ADDR(v) (v) argument
388 #define BF_PXP_PS_BUF_ADDR(v) (v) argument
394 #define BF_PXP_PS_UBUF_ADDR(v) (v) argument
400 #define BF_PXP_PS_VBUF_ADDR(v) (v) argument
545 #define BF_PXP_AS_BUF_ADDR(v) (v) argument
846 #define BF_PXP_LUT_DATA_DATA(v) (v) argument
852 #define BF_PXP_LUT_EXTMEM_ADDR(v) (v) argument
858 #define BF_PXP_CFA_DATA(v) (v) argument
1486 #define BF_PXP_INIT_MEM_DATA_DATA(v) (v) argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c1938 v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2144 …v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / … in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2145 …v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] … in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2227 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2460 v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2463 …v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->Writebac… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4080 …if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[… in dml30_ModeSupportAndSystemConfigurationFull()
4429 …v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HT… in dml30_ModeSupportAndSystemConfigurationFull()
5026 …v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v… in dml30_ModeSupportAndSystemConfigurationFull()
5275 …if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] || v->AlignedDCCMetaP… in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c2124 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
2401 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
2657 v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
3272 v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
3335 (int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
3988 || v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
4038 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
4128 v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
4144 v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
5667 if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
[all …]
/linux/drivers/staging/media/hantro/
A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
50 #define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) argument
57 #define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) argument
59 #define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) argument
64 #define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) argument
73 #define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) argument
[all …]
A Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
42 #define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) argument
43 #define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) argument
44 #define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) argument
51 #define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) argument
54 #define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0) argument
64 #define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) argument
[all …]
A Dhantro_g1_mpeg2_dec.c26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
35 #define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0) argument
37 #define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0) argument
41 #define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0) argument
44 #define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0) argument
54 #define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) argument
[all …]
/linux/drivers/iio/adc/
A Dstm32-dfsdm.h111 #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v) argument
133 #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v) argument
135 #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v) argument
141 #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v) argument
157 #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v) argument
171 #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v) argument
173 #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v) argument
175 #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v) argument
179 #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v) argument
199 #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v) argument
[all …]
/linux/drivers/gpu/host1x/hw/
A Dhw_host1x01_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x02_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x04_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x05_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x06_uclass.h50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x07_uclass.h50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
/linux/drivers/md/
A Ddm-verity-target.c147 if (likely(v->salt_size && (v->version >= 1))) in verity_hash_init()
148 r = verity_hash_update(v, req, v->salt, v->salt_size, wait); in verity_hash_init()
158 if (unlikely(v->salt_size && (!v->version))) { in verity_hash_final()
159 r = verity_hash_update(v, req, v->salt, v->salt_size, wait); in verity_hash_final()
301 r = verity_hash(v, verity_io_hash_req(v, io), in verity_verify_level()
475 struct dm_verity *v = io->v; in verity_verify_io() local
564 struct dm_verity *v = io->v; in verity_finish_io() local
605 struct dm_verity *v = pw->v; in verity_prefetch_io() local
661 pw->v = v; in verity_submit_prefetch()
695 io->v = v; in verity_map()
[all …]
/linux/arch/sh/mm/
A Dflush-sh4.c25 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
26 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
27 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
28 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
29 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
30 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
31 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
32 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
37 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
59 __ocbp(v); v += L1_CACHE_BYTES; in sh4__flush_purge_region()
[all …]
/linux/sound/soc/qcom/
A Dlpass-lpaif-reg.h12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
69 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
73 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) argument
74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) argument
75 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) argument
98 (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
110 (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
114 #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan)) argument
118 #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) argument
[all …]
/linux/arch/x86/lib/
A Datomic64_386_32.S27 LOCK v;
44 #undef v
51 #undef v
60 #undef v
67 #undef v
76 #undef v
83 #undef v
95 #undef v
102 #undef v
113 #undef v
[all …]
/linux/arch/ia64/include/asm/
A Datomic.h24 #define arch_atomic_read(v) READ_ONCE((v)->counter) argument
25 #define arch_atomic64_read(v) READ_ONCE((v)->counter) argument
27 #define arch_atomic_set(v,i) WRITE_ONCE(((v)->counter), (i)) argument
28 #define arch_atomic64_set(v,i) WRITE_ONCE(((v)->counter), (i)) argument
113 #define arch_atomic_and(i,v) (void)ia64_atomic_fetch_and(i,v) argument
114 #define arch_atomic_or(i,v) (void)ia64_atomic_fetch_or(i,v) argument
115 #define arch_atomic_xor(i,v) (void)ia64_atomic_fetch_xor(i,v) argument
117 #define arch_atomic_fetch_and(i,v) ia64_atomic_fetch_and(i,v) argument
118 #define arch_atomic_fetch_or(i,v) ia64_atomic_fetch_or(i,v) argument
119 #define arch_atomic_fetch_xor(i,v) ia64_atomic_fetch_xor(i,v) argument
[all …]
/linux/drivers/gpu/drm/exynos/
A Dregs-scaler.h244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
268 #define SCALER_DST_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
270 #define SCALER_DST_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
274 #define SCALER_DST_POS_SET_H_POS(v) SCALER_SET(v, 29, 16) argument
276 #define SCALER_DST_POS_SET_V_POS(v) SCALER_SET(v, 13, 0) argument
280 #define SCALER_H_RATIO_SET(v) SCALER_SET(v, 18, 0) argument
284 #define SCALER_V_RATIO_SET(v) SCALER_SET(v, 18, 0) argument
290 #define SCALER_ROT_CFG_SET_ROTMODE(v) SCALER_SET(v, 1, 0) argument
304 #define SCALER_CSC_COEF_SET(v) SCALER_SET(v, 11, 0) argument
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
A Dcedrus_regs.h105 ((v) ? BIT(7) : 0)
107 ((v) ? BIT(6) : 0)
109 ((v) ? BIT(5) : 0)
660 #define VE_VP8_SEGMENT3(v) SHIFT_AND_MASK_BITS(v, 31, 24) argument
661 #define VE_VP8_SEGMENT2(v) SHIFT_AND_MASK_BITS(v, 23, 16) argument
662 #define VE_VP8_SEGMENT1(v) SHIFT_AND_MASK_BITS(v, 15, 8) argument
663 #define VE_VP8_SEGMENT0(v) SHIFT_AND_MASK_BITS(v, 7, 0) argument
668 #define VE_VP8_LF_DELTA3(v) SHIFT_AND_MASK_BITS(v, 30, 24) argument
669 #define VE_VP8_LF_DELTA2(v) SHIFT_AND_MASK_BITS(v, 22, 16) argument
670 #define VE_VP8_LF_DELTA1(v) SHIFT_AND_MASK_BITS(v, 14, 8) argument
[all …]
/linux/arch/powerpc/include/asm/
A Datomic.h131 : "r" (&v->counter) in ATOMIC_OPS()
146 : "r" (&v->counter) in arch_atomic_inc_return_relaxed()
162 : "r" (&v->counter) in arch_atomic_dec()
177 : "r" (&v->counter) in arch_atomic_dec_return_relaxed()
281 : "r" (&v->counter) in arch_atomic_inc_not_zero()
286 #define arch_atomic_inc_not_zero(v) arch_atomic_inc_not_zero((v)) argument
308 : "r" (&v->counter) in arch_atomic_dec_if_positive()
426 : "r" (&v->counter) in ATOMIC64_OPS()
441 : "r" (&v->counter) in arch_atomic64_inc_return_relaxed()
457 : "r" (&v->counter) in arch_atomic64_dec()
[all …]

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