Searched refs:vclk_div (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/gpu/drm/meson/ |
| A D | meson_vclk.c | 372 unsigned int vclk_div; member
384 .vclk_div = 1,
396 .vclk_div = 1,
408 .vclk_div = 1,
420 .vclk_div = 1,
432 .vclk_div = 1,
444 .vclk_div = 2,
456 .vclk_div = 1,
468 .vclk_div = 1,
810 unsigned int vid_pll_div, unsigned int vclk_div, in meson_vclk_set() argument
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| /linux/drivers/gpu/drm/radeon/ |
| A D | radeon_uvd.c | 981 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
992 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
994 if (vclk_div > pd_max) in radeon_uvd_calc_upll_dividers()
1004 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
1009 *optimal_vclk_div = vclk_div; in radeon_uvd_calc_upll_dividers()
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| A D | rv770.c | 55 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
75 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
80 vclk_div -= 1; in rv770_set_uvd_clocks()
103 UPLL_SW_HILEN(vclk_div >> 1) | in rv770_set_uvd_clocks()
104 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in rv770_set_uvd_clocks()
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| A D | r600.c | 205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
261 UPLL_SW_HILEN(vclk_div >> 1) | in r600_set_uvd_clocks()
262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in r600_set_uvd_clocks()
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| A D | evergreen.c | 1190 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1209 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1248 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
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| A D | si.c | 6992 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7010 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7051 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | si.c | 1732 unsigned vclk_div, dclk_div, score; in si_calc_upll_dividers() local
1743 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1745 if (vclk_div > pd_max) in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1760 *optimal_vclk_div = vclk_div; in si_calc_upll_dividers()
1777 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1795 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1838 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
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