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Searched refs:vlv_punit_read (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
A Dintel_rps.c1113 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1140 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1151 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1161 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1200 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1259 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1301 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
1530 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_init()
1945 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in read_cagf()
A Dintel_gt_pm_debugfs.c316 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in intel_gt_pm_frequency_dump()
/linux/drivers/gpu/drm/i915/
A Dvlv_sideband.h115 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
A Dvlv_sideband.c124 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
A Dintel_pm.c342 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
351 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
365 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
6964 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
6977 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
6981 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
6988 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
/linux/drivers/gpu/drm/i915/display/
A Dintel_display_power.c1307 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1312 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1321 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1355 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1369 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1872 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1885 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1906 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1911 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1920 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
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A Dintel_cdclk.c519 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
602 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
606 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
686 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
690 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()

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