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Searched refs:wait_for (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/mmc/host/
A Dsh_mmcif.c234 enum sh_mmcif_wait_for wait_for; member
588 host->state, host->wait_for); in sh_mmcif_error_manage()
592 host->state, host->wait_for); in sh_mmcif_error_manage()
596 host->state, host->wait_for); in sh_mmcif_error_manage()
628 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
942 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
965 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
1185 wait_work = host->wait_for; in sh_mmcif_irqt()
1195 host->state, host->wait_for); in sh_mmcif_irqt()
1337 host->wait_for, mrq->cmd->opcode); in sh_mmcif_timeout_work()
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/linux/drivers/gpu/drm/v3d/
A Dv3d_mmu.c40 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & in v3d_mmu_flush_all()
52 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & in v3d_mmu_flush_all()
59 ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) & in v3d_mmu_flush_all()
A Dv3d_gem.c52 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) & in v3d_idle_axi()
68 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & in v3d_idle_gca()
199 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & in v3d_clean_caches()
209 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & in v3d_clean_caches()
A Dv3d_drv.h338 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) macro
/linux/drivers/gpu/drm/gma500/
A Dintel_gmbus.c53 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
279 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
308 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
325 …if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PH… in gmbus_xfer()
A Dcdv_intel_display.c126 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
A Dcdv_intel_dp.c250 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
432 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
466 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { in cdv_intel_edp_panel_off()
/linux/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_fw.c93 ret = wait_for(guc_ready(uncore, &status), 100); in guc_wait_ucode()
A Dintel_guc_slpc.c262 if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) { in slpc_reset()
A Dintel_guc.c445 ret = wait_for(done, 1000); in intel_guc_send_mmio()
/linux/drivers/gpu/drm/i915/gt/
A Dselftest_rps.c188 if (wait_for(!intel_rps_set(rps, freq), 50)) { in rps_set_check()
284 if (wait_for(intel_uncore_read_fw(gt->uncore, in live_rps_clock_interval()
664 if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)), in live_rps_frequency_cs()
805 if (wait_for(READ_ONCE(*cntr), 10)) { in live_rps_frequency_srm()
A Dselftest_hangcheck.c292 wait_for(i915_seqno_passed(hws_seqno(h, rq), in wait_until_running()
358 return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0; in wait_for_idle()
1544 if (wait_for(!list_empty(&rq->fence.cb_list), 10)) { in __igt_reset_evict_vma()
/linux/drivers/gpu/drm/i915/selftests/
A Di915_request.c1869 if (wait_for(READ_ONCE(*sema) == 0, 50)) { in measure_semaphore_response()
1880 if (wait_for(READ_ONCE(*sema) == 0, 50)) { in measure_semaphore_response()
2014 if (i > 1 && wait_for(READ_ONCE(sema[i - 1]), 500)) { in measure_busy_dispatch()
2028 wait_for(READ_ONCE(sema[i - 1]), 500); in measure_busy_dispatch()
2311 if (wait_for(READ_ONCE(sema[2 * i]) == -1, 500)) { in measure_preemption()
2339 if (wait_for(READ_ONCE(sema[2 * i - 2]) != -1, 500)) { in measure_preemption()
2426 if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { in measure_completion()
A Digt_spinner.c273 wait_for(i915_seqno_passed(hws_seqno(spin, rq), in igt_wait_for_spinner()
A Dintel_uncore.c257 if (wait_for(readl(reg) == 0, 100)) { in live_forcewake_ops()
/linux/drivers/gpu/drm/i915/display/
A Dintel_dsb.c242 if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { in intel_dsb_commit()
A Dintel_lspcon.c166 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); in lspcon_wait_mode()
A Dvlv_dsi_pll.c169 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & in vlv_dsi_pll_enable()
/linux/drivers/gpu/drm/vc4/
A Dvc4_hdmi.c374 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & in vc4_hdmi_stop_packet()
423 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & in vc4_hdmi_write_infoframe()
865 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & in vc4_hdmi_recenter_fifo()
1034 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & in vc4_hdmi_encoder_post_crtc_enable()
1046 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & in vc4_hdmi_encoder_post_crtc_enable()
A Dvc4_dsi.c707 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200); in vc4_dsi_ulps()
726 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200); in vc4_dsi_ulps()
A Dvc4_drv.h783 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) macro
/linux/drivers/gpu/drm/i915/
A Di915_utils.h344 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) macro
A Dvlv_suspend.c295 ret = wait_for(((reg_value = in vlv_wait_for_pw_status()
A Di915_debugfs.c638 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) in gt_drop_caches()
/linux/drivers/scsi/
A Dscsi_lib.c631 unsigned long wait_for; in scsi_cmd_runtime_exceeced() local
636 wait_for = (cmd->allowed + 1) * req->timeout; in scsi_cmd_runtime_exceeced()
637 if (time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) { in scsi_cmd_runtime_exceeced()
639 wait_for/HZ); in scsi_cmd_runtime_exceeced()

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