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Searched refs:wm_table (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_build_wm_range_table()
143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
149 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn3_build_wm_range_table()
151 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_build_wm_range_table()
154 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
157 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c475 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
626 static struct wm_table ddr4_wm_table_gs = {
663 static struct wm_table lpddr4_wm_table_gs = {
737 static struct wm_table ddr4_wm_table_rn = {
774 static struct wm_table ddr4_1R_wm_table_rn = {
811 static struct wm_table lpddr4_wm_table_rn = {
912 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
915 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
920 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
996 rn_bw_params.wm_table = ddr4_wm_table_gs; in rn_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c406 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
542 static struct wm_table ddr4_wm_table = {
579 static struct wm_table lpddr5_wm_table = {
671 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
674 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
678 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()
679 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
687 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in vg_clk_mgr_helper_populate_bw_params()
689 bw_params->wm_table.entries[WM_D].valid = true; in vg_clk_mgr_helper_populate_bw_params()
794 vg_bw_params.wm_table = lpddr5_wm_table; in vg_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c332 static struct wm_table ddr4_wm_table = {
369 static struct wm_table lpddr5_wm_table = {
418 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
421 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
607 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
610 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
614 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()
615 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()
689 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h199 struct wm_table { struct
215 struct wm_table wm_table; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c347 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg()
355 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_calculate_wm_and_dlg()
360 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_calculate_wm_and_dlg()
366 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_calculate_wm_and_dlg()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1847 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
1848 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
1849 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
1850 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
1883 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn31_calculate_wm_and_dlg_fp()
1888 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
1890 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn31_calculate_wm_and_dlg_fp()
1909 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn31_calculate_wm_and_dlg_fp()
1912 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn31_calculate_wm_and_dlg_fp()
1928 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { in dcn31_calculate_wm_and_dlg_fp()
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/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2147 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg_fp()
2152 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg_fp()
2153 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()
2154 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_calculate_wm_and_dlg_fp()
2194 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg_fp()
2207 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()
2208 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_calculate_wm_and_dlg_fp()
2273 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()
2278 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_update_soc_for_wm_a()
2279 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_update_soc_for_wm_a()
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1072 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
1079 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
1090 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
1156 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
1164 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
1169 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()
1175 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c2532 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local
2537 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
A Dvega20_hwmgr.c3643 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local
3648 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
A Dvega10_hwmgr.c4763 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local
4768 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()

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