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Searched refs:wptr (Results 1 – 25 of 100) sorted by relevance

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/linux/drivers/media/usb/pvrusb2/
A Dpvrusb2-debugifc.c55 const char *wptr; in debugifc_isolate_word() local
60 wptr = NULL; in debugifc_isolate_word()
68 wptr = buf; in debugifc_isolate_word()
73 *wstrPtr = wptr; in debugifc_isolate_word()
182 const char *wptr; in pvr2_debugifc_do1cmd() local
189 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
196 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
223 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
226 if (scnt && wptr) { in pvr2_debugifc_do1cmd()
256 if (!wptr) return -EINVAL; in pvr2_debugifc_do1cmd()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.c151 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write() local
155 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
157 wptr <<= 2; in amdgpu_ih_ring_write()
158 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
161 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
163 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
227 u32 wptr; in amdgpu_ih_process() local
232 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
241 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
250 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
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A Diceland_ih.c193 u32 wptr, tmp; in iceland_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
220 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
A Dcz_ih.c193 u32 wptr, tmp; in cz_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
221 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
A Dtonga_ih.c195 u32 wptr, tmp; in tonga_ih_get_wptr() local
197 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
208 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
223 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
A Dcik_ih.c191 u32 wptr, tmp; in cik_ih_get_wptr() local
193 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
195 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
196 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
208 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
A Dsi_ih.c110 u32 wptr, tmp; in si_ih_get_wptr() local
112 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
114 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
115 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
123 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
A Dvega10_ih.c334 u32 wptr, tmp; in vega10_ih_get_wptr() local
341 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
343 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
350 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
351 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
354 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
360 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
363 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
371 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
A Dsdma_v5_2.c224 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_2_ring_patch_cond_exec()
259 u64 wptr; in sdma_v5_2_ring_get_wptr() local
267 wptr = wptr << 32; in sdma_v5_2_ring_get_wptr()
272 return wptr >> 2; in sdma_v5_2_ring_get_wptr()
293 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
294 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
306 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
308 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
310 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
312 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
[all …]
A Dvcn_v2_0.c911 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode()
913 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1071 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1227 ring->wptr = 0; in vcn_v2_0_pause_dpg_mode()
1237 ring->wptr = 0; in vcn_v2_0_pause_dpg_mode()
1351 lower_32_bits(ring->wptr) | 0x80000000); in vcn_v2_0_dec_ring_set_wptr()
1406 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v2_0_dec_ring_insert_nop()
1809 adev->vcn.inst->ring_dec.wptr = 0; in vcn_v2_0_start_mmsch()
1814 adev->vcn.inst->ring_enc[i].wptr = 0; in vcn_v2_0_start_mmsch()
1941 ring->wptr = 0; in vcn_v2_0_start_sriov()
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A Dvcn_v3_0.c300 ring->wptr = 0; in vcn_v3_0_hw_init()
312 ring->wptr = 0; in vcn_v3_0_hw_init()
1062 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
1066 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start_dpg_mode()
1238 lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1239 fw_shared->rb.wptr = lower_32_bits(ring->wptr); in vcn_v3_0_start()
1377 ring->wptr = 0; in vcn_v3_0_start_sriov()
1391 ring->wptr = 0; in vcn_v3_0_start_sriov()
1617 ring->wptr = 0; in vcn_v3_0_pause_dpg_mode()
1627 ring->wptr = 0; in vcn_v3_0_pause_dpg_mode()
[all …]
A Dvega20_ih.c385 u32 wptr, tmp; in vega20_ih_get_wptr() local
392 wptr = le32_to_cpu(*ih->wptr_cpu); in vega20_ih_get_wptr()
394 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega20_ih_get_wptr()
401 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
402 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega20_ih_get_wptr()
405 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega20_ih_get_wptr()
411 tmp = (wptr + 32) & ih->ptr_mask; in vega20_ih_get_wptr()
414 wptr, ih->rptr, tmp); in vega20_ih_get_wptr()
422 return (wptr & ih->ptr_mask); in vega20_ih_get_wptr()
A Dsdma_v4_0.c741 u64 wptr; in sdma_v4_0_ring_get_wptr() local
749 wptr = wptr << 32; in sdma_v4_0_ring_get_wptr()
752 ring->me, wptr); in sdma_v4_0_ring_get_wptr()
755 return wptr >> 2; in sdma_v4_0_ring_get_wptr()
810 u64 wptr; in sdma_v4_0_page_ring_get_wptr() local
817 wptr = wptr << 32; in sdma_v4_0_page_ring_get_wptr()
821 return wptr >> 2; in sdma_v4_0_page_ring_get_wptr()
842 uint64_t wptr = ring->wptr << 2; in sdma_v4_0_page_ring_set_wptr() local
845 lower_32_bits(wptr)); in sdma_v4_0_page_ring_set_wptr()
1206 ring->wptr = 0; in sdma_v4_0_gfx_resume()
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A Dnavi10_ih.c409 u32 wptr, tmp; in navi10_ih_get_wptr() local
416 wptr = le32_to_cpu(*ih->wptr_cpu); in navi10_ih_get_wptr()
418 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
425 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
426 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
428 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in navi10_ih_get_wptr()
434 tmp = (wptr + 32) & ih->ptr_mask; in navi10_ih_get_wptr()
437 wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
444 return (wptr & ih->ptr_mask); in navi10_ih_get_wptr()
A Dsdma_v5_0.c337 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_0_ring_patch_cond_exec()
372 u64 wptr; in sdma_v5_0_ring_get_wptr() local
380 wptr = wptr << 32; in sdma_v5_0_ring_get_wptr()
385 return wptr >> 2; in sdma_v5_0_ring_get_wptr()
406 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
407 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
419 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
421 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
423 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
425 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
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A Dvcn_v2_5.c890 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
892 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
1068 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1070 lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1245 ring->wptr = 0; in vcn_v2_5_sriov_start()
1258 ring->wptr = 0; in vcn_v2_5_sriov_start()
1425 ring->wptr = 0; in vcn_v2_5_pause_dpg_mode()
1435 ring->wptr = 0; in vcn_v2_5_pause_dpg_mode()
1505 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1626 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
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/linux/drivers/net/ppp/
A Dbsd_comp.c586 if (wptr) \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
893 wptr = obuf; in bsd_decompress()
894 *wptr++ = adrs; in bsd_decompress()
895 *wptr++ = ctrl; in bsd_decompress()
896 *wptr++ = 0; in bsd_decompress()
994 wptr += codelen; in bsd_decompress()
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A Dppp_deflate.c190 unsigned char *wptr; in z_compress() local
204 wptr = obuf; in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
211 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
212 wptr += PPP_HDRLEN; in z_compress()
213 put_unaligned_be16(state->seqno, wptr); in z_compress()
214 wptr += DEFLATE_OVHD; in z_compress()
216 state->strm.next_out = wptr; in z_compress()
/linux/drivers/net/ethernet/tehuti/
A Dtehuti.c171 f->wptr = 0; in bdx_fifo_init()
1112 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1167 f->m.wptr = delta; in bdx_recycle_skb()
1210 size = f->m.wptr - f->m.rptr; in bdx_rx_receive()
1427 d->wptr = d->start; in bdx_tx_db_init()
1505 db->wptr->addr.skb = skb; in bdx_tx_map_skb()
1568 fsize = f->m.rptr - f->m.wptr; in bdx_tx_space()
1639 len = f->m.wptr - f->m.memsz; in bdx_tx_transmit()
1641 f->m.wptr = len; in bdx_tx_transmit()
1806 f->m.wptr += size; in bdx_tx_push_desc()
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_kernel_queue.c232 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
242 wptr = kq->pending_wptr; in kq_acquire_packet_buffer()
248 pr_debug("wptr: %d\n", wptr); in kq_acquire_packet_buffer()
251 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
262 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in kq_acquire_packet_buffer()
270 while (wptr > 0) { in kq_acquire_packet_buffer()
271 queue_address[wptr] = kq->nop_packet; in kq_acquire_packet_buffer()
272 wptr = (wptr + 1) % queue_size_dwords; in kq_acquire_packet_buffer()
277 *buffer_ptr = &queue_address[wptr]; in kq_acquire_packet_buffer()
278 kq->pending_wptr = wptr + packet_size_in_dwords; in kq_acquire_packet_buffer()
/linux/drivers/gpu/drm/radeon/
A Dradeon_ring.c87 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
128 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
176 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
214 ring->wptr = ring->wptr_old; in radeon_ring_undo()
314 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
470 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
476 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show()
478 wptr, wptr); in radeon_debugfs_ring_info_show()
492 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/linux/drivers/crypto/ccp/
A Dtee-dev.c124 tee->rb_mgr.wptr = 0; in tee_init_ring()
259 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd()
266 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
271 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
281 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
284 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
307 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd()
308 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd()
309 tee->rb_mgr.wptr = 0; in tee_submit_cmd()
312 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
/linux/drivers/gpu/drm/msm/adreno/
A Dadreno_gpu.c468 uint32_t wptr; in adreno_flush() local
478 wptr = get_wptr(ring); in adreno_flush()
483 gpu_write(gpu, reg, wptr); in adreno_flush()
489 uint32_t wptr = get_wptr(ring); in adreno_idle() local
492 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) in adreno_idle()
497 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); in adreno_idle()
518 state->ring[i].wptr = get_wptr(gpu->rb[i]); in adreno_gpu_state_get()
521 size = state->ring[i].wptr; in adreno_gpu_state_get()
713 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); in adreno_show()
801 uint32_t wptr = ring->next - ring->start; in ring_freewords() local
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/linux/drivers/video/fbdev/
A Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()

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