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Searched refs:wr32 (Results 1 – 25 of 91) sorted by relevance

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/linux/drivers/net/ethernet/intel/igc/
A Digc_tsn.c66 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_disable_offload()
69 wr32(IGC_TXQCTL(i), 0); in igc_tsn_disable_offload()
70 wr32(IGC_STQT(i), 0); in igc_tsn_disable_offload()
74 wr32(IGC_QBVCYCLET_S, 0); in igc_tsn_disable_offload()
93 wr32(IGC_TSAUXC, 0); in igc_tsn_enable_offload()
99 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_enable_offload()
101 wr32(IGC_QBVCYCLET_S, cycle); in igc_tsn_enable_offload()
102 wr32(IGC_QBVCYCLET, cycle); in igc_tsn_enable_offload()
194 wr32(IGC_TQAVHC(i), in igc_tsn_enable_offload()
207 wr32(IGC_TQAVHC(i), 0); in igc_tsn_enable_offload()
[all …]
A Digc_base.c32 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
34 wr32(IGC_RCTL, 0); in igc_reset_hw_base()
35 wr32(IGC_TCTL, IGC_TCTL_PSP); in igc_reset_hw_base()
55 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
116 wr32(IGC_CTRL, ctrl); in igc_setup_copper_link_base()
342 wr32(IGC_RFCTL, rfctl); in igc_rx_fifo_flush_base()
350 wr32(IGC_RXDCTL(i), in igc_rx_fifo_flush_base()
373 wr32(IGC_RLPML, 0); in igc_rx_fifo_flush_base()
389 wr32(IGC_RCTL, rctl); in igc_rx_fifo_flush_base()
392 wr32(IGC_RLPML, rlpml); in igc_rx_fifo_flush_base()
[all …]
A Digc_ptp.c68 wr32(IGC_TIMINCA, inca); in igc_ptp_adjfine_i225()
205 wr32(IGC_TSSDP, tssdp); in igc_pin_perout()
206 wr32(IGC_CTRL, ctrl); in igc_pin_perout()
242 wr32(IGC_CTRL, ctrl); in igc_pin_extts()
298 wr32(IGC_TSIM, tsim); in igc_ptp_feature_enable_i225()
369 wr32(freqout, ns); in igc_ptp_feature_enable_i225()
374 wr32(IGC_TSIM, tsim); in igc_ptp_feature_enable_i225()
386 wr32(IGC_TSIM, tsim); in igc_ptp_feature_enable_i225()
507 wr32(IGC_RXPBS, val); in igc_ptp_disable_rx_timestamp()
518 wr32(IGC_RXPBS, val); in igc_ptp_enable_rx_timestamp()
[all …]
A Digc_diag.c46 wr32(reg, test_pattern[pat] & write); in reg_pattern_test()
53 wr32(reg, before); in reg_pattern_test()
56 wr32(reg, before); in reg_pattern_test()
68 wr32(reg, write & mask); in reg_set_and_check()
75 wr32(reg, before); in reg_set_and_check()
78 wr32(reg, before); in reg_set_and_check()
97 wr32(IGC_STATUS, toggle); in igc_reg_test()
107 wr32(IGC_STATUS, before); in igc_reg_test()
A Digc_mac.c29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
103 wr32(IGC_FCRTL, fcrtl); in igc_set_fc_watermarks()
104 wr32(IGC_FCRTH, fcrth); in igc_set_fc_watermarks()
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE); in igc_setup_link()
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igc_setup_link()
158 wr32(IGC_FCTTV, hw->fc.pause_time); in igc_setup_link()
223 wr32(IGC_CTRL, ctrl); in igc_force_mac_fc()
341 wr32(IGC_RAL(index), rar_low); in igc_rar_set()
343 wr32(IGC_RAH(index), rar_high); in igc_rar_set()
438 wr32(IGC_TCTL, tctl); in igc_config_collision_dist()
[all …]
A Digc_i225.c82 wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_i225()
140 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_acquire_swfw_sync_i225()
164 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_release_swfw_sync_i225()
241 wr32(IGC_SRWR, eewr); in igc_write_nvm_srwr()
376 wr32(IGC_EECD, flup); in igc_update_flash_i225()
539 wr32(IGC_IPCNFG, ipcnfg); in igc_set_eee_i225()
540 wr32(IGC_EEER, eeer); in igc_set_eee_i225()
572 wr32(IGC_LTRC, ltrc); in igc_set_ltr_i225()
633 wr32(IGC_LTRMINV, ltrv); in igc_set_ltr_i225()
640 wr32(IGC_LTRMAXV, ltrv); in igc_set_ltr_i225()
A Digc_main.c160 wr32(IGC_CTRL_EXT, in igc_release_hw_control()
179 wr32(IGC_CTRL_EXT, in igc_get_hw_control()
790 wr32(IGC_MRQC, mrqc); in igc_setup_mrqc()
837 wr32(IGC_RCTL, rctl); in igc_setup_rctl()
861 wr32(IGC_TCTL, tctl); in igc_setup_tctl()
3808 wr32(IGC_IAM, 0); in igc_irq_disable()
3809 wr32(IGC_IMC, ~0); in igc_irq_disable()
6570 wr32(IGC_WUC, 0); in __igc_shutdown()
6571 wr32(IGC_WUFC, 0); in __igc_shutdown()
6669 wr32(IGC_WUS, ~0); in igc_resume()
[all …]
A Digc_nvm.c52 wr32(IGC_EECD, eecd | IGC_EECD_REQ); in igc_acquire_nvm()
65 wr32(IGC_EECD, eecd); in igc_acquire_nvm()
85 wr32(IGC_EECD, eecd); in igc_release_nvm()
117 wr32(IGC_EERD, eerd); in igc_read_nvm_eerd()
/linux/drivers/net/ethernet/intel/igb/
A Digb_ptp.c244 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfine_82580()
439 wr32(E1000_TSSDP, tssdp); in igb_pin_extts()
440 wr32(E1000_CTRL, ctrl); in igb_pin_extts()
505 wr32(E1000_TSSDP, tssdp); in igb_pin_perout()
506 wr32(E1000_CTRL, ctrl); in igb_pin_perout()
562 wr32(E1000_TSIM, tsim); in igb_ptp_feature_enable_i210()
631 wr32(freqout, ns); in igb_ptp_feature_enable_i210()
636 wr32(E1000_TSIM, tsim); in igb_ptp_feature_enable_i210()
648 wr32(E1000_TSIM, tsim); in igb_ptp_feature_enable_i210()
1135 wr32(E1000_IMIREXT(3), in igb_ptp_set_timestamp_mode()
[all …]
A De1000_82575.c1471 wr32(E1000_RCTL, 0); in igb_reset_hw_82575()
1577 wr32(E1000_CTRL, ctrl); in igb_setup_copper_link_82575()
1689 wr32(E1000_CONNSW, reg); in igb_setup_serdes_link_82575()
1953 wr32(E1000_RFCTL, rfctl); in igb_rx_fifo_flush_82575()
1962 wr32(E1000_RXDCTL(i), in igb_rx_fifo_flush_82575()
1985 wr32(E1000_RLPML, 0); in igb_rx_fifo_flush_82575()
2001 wr32(E1000_RCTL, rctl); in igb_rx_fifo_flush_82575()
2058 wr32(E1000_GCR, gcr); in igb_set_pcie_completion_timeout()
2278 wr32(E1000_RCTL, 0); in igb_reset_hw_82580()
2295 wr32(E1000_CTRL, ctrl); in igb_reset_hw_82580()
[all …]
A De1000_mac.c243 wr32(E1000_VLVF(vlvf_index), 0); in igb_vfta_set()
377 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
379 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
746 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
779 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
780 wr32(E1000_FCRTH, fcrth); in igb_set_fc_watermarks()
884 wr32(E1000_CTRL, ctrl); in igb_force_mac_fc()
1325 wr32(E1000_SWSM, swsm); in igb_put_hw_semaphore()
1514 wr32(E1000_LEDCTL, ledctl_blink); in igb_blink_led()
1560 wr32(E1000_CTRL, ctrl); in igb_disable_pcie_master()
[all …]
A De1000_i210.c148 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
172 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
250 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
679 wr32(E1000_EECD, flup); in igb_update_flash_i210()
837 wr32(E1000_MDICNFG, reg_val); in igb_pll_workaround_i210()
863 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pll_workaround_i210()
865 wr32(E1000_WUC, 0); in igb_pll_workaround_i210()
867 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
876 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
879 wr32(E1000_WUC, wuc); in igb_pll_workaround_i210()
[all …]
A Digb_main.c1491 wr32(E1000_IAM, 0); in igb_irq_disable()
1492 wr32(E1000_IMC, ~0); in igb_irq_disable()
1571 wr32(E1000_CTRL_EXT, in igb_release_hw_control()
1590 wr32(E1000_CTRL_EXT, in igb_get_hw_control()
2358 wr32(E1000_VFRE, 0); in igb_reset()
2359 wr32(E1000_VFTE, 0); in igb_reset()
2364 wr32(E1000_WUC, 0); in igb_reset()
4604 wr32(reg, val); in igb_set_vf_vlan_strip()
6459 wr32(E1000_EICS, in igb_tx_timeout()
9199 wr32(E1000_WUC, 0); in __igb_shutdown()
[all …]
A De1000_nvm.c20 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
35 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
66 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
78 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
165 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
178 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
200 wr32(E1000_EECD, eecd); in igb_standby_nvm()
204 wr32(E1000_EECD, eecd); in igb_standby_nvm()
242 wr32(E1000_EECD, eecd); in igb_release_nvm()
263 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
A De1000_mbx.c249 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
307 wr32(E1000_VFLRE, BIT(vf_number)); in igb_check_for_rst_pf()
329 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
357 wr32(E1000_P2VMAILBOX(vf_number), in igb_release_mbx_lock_pf()
392 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
431 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
433 wr32(E1000_P2VMAILBOX(vf_number), in igb_read_mbx_pf()
A Digb_ethtool.c1243 wr32(reg, write & mask); in reg_set_and_check()
1435 wr32(E1000_IMC, ~0); in igb_intr_test()
1479 wr32(E1000_ICR, ~0); in igb_intr_test()
1501 wr32(E1000_ICR, ~0); in igb_intr_test()
1503 wr32(E1000_IMS, mask); in igb_intr_test()
1504 wr32(E1000_ICS, mask); in igb_intr_test()
1523 wr32(E1000_ICR, ~0); in igb_intr_test()
1538 wr32(E1000_IMC, ~0); in igb_intr_test()
1704 wr32(E1000_RCTL, reg); in igb_setup_loopback_test()
1714 wr32(E1000_CTRL, reg); in igb_setup_loopback_test()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
A Di40e_ptp.c394 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0); in i40e_ptp_set_1pps_signal_hw()
409 wr32(hw, I40E_PRTTSYN_AUX_0(1), in i40e_ptp_set_1pps_signal_hw()
442 wr32(hw, I40E_PRTTSYN_ADJ, timadj); in i40e_ptp_adjtime()
984 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), in i40e_ptp_set_pin_hw()
988 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), in i40e_ptp_set_pin_hw()
992 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), in i40e_ptp_set_pin_hw()
996 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), in i40e_ptp_set_pin_hw()
1018 wr32(hw, I40E_GLGEN_GPIO_SET, in i40e_ptp_set_led_hw()
1022 wr32(hw, I40E_GLGEN_GPIO_SET, in i40e_ptp_set_led_hw()
1204 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_set_timestamp_mode()
[all …]
A Di40e_hmc.h108 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
109 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
110 wr32((hw), I40E_PFHMC_SDCMD, val3); \
127 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
128 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
129 wr32((hw), I40E_PFHMC_SDCMD, val3); \
139 wr32((hw), I40E_PFHMC_PDINV, \
A Di40e_adminq.c275 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
276 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
304 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
305 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
460 wr32(hw, hw->aq.asq.head, 0); in i40e_shutdown_asq()
462 wr32(hw, hw->aq.asq.len, 0); in i40e_shutdown_asq()
463 wr32(hw, hw->aq.asq.bal, 0); in i40e_shutdown_asq()
464 wr32(hw, hw->aq.asq.bah, 0); in i40e_shutdown_asq()
496 wr32(hw, hw->aq.arq.len, 0); in i40e_shutdown_arq()
497 wr32(hw, hw->aq.arq.bal, 0); in i40e_shutdown_arq()
[all …]
A Di40e_dcb.c1338 wr32(hw, I40E_PRTDCB_RETSC, reg); in i40e_dcb_hw_rx_fifo_config()
1400 wr32(hw, I40E_PRTDCB_RPPMC, reg); in i40e_dcb_hw_rx_cmd_monitor_config()
1509 wr32(hw, I40E_PRTDCB_RUP, reg); in i40e_dcb_hw_pfc_config()
1517 wr32(hw, I40E_PRTDCB_TDPMC, reg); in i40e_dcb_hw_pfc_config()
1525 wr32(hw, I40E_PRTDCB_TCPMC, reg); in i40e_dcb_hw_pfc_config()
1542 wr32(hw, I40E_PRTDCB_GENC, reg); in i40e_dcb_hw_set_num_tc()
1727 wr32(hw, I40E_PRTRPB_SLW, reg); in i40e_dcb_hw_rx_pb_config()
1763 wr32(hw, I40E_PRTRPB_SHW, reg); in i40e_dcb_hw_rx_pb_config()
1807 wr32(hw, I40E_PRTRPB_SPS, reg); in i40e_dcb_hw_rx_pb_config()
1817 wr32(hw, I40E_PRTRPB_SLW, reg); in i40e_dcb_hw_rx_pb_config()
[all …]
/linux/drivers/net/ethernet/intel/iavf/
A Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
447 wr32(hw, hw->aq.asq.head, 0); in iavf_shutdown_asq()
449 wr32(hw, hw->aq.asq.len, 0); in iavf_shutdown_asq()
450 wr32(hw, hw->aq.asq.bal, 0); in iavf_shutdown_asq()
451 wr32(hw, hw->aq.asq.bah, 0); in iavf_shutdown_asq()
483 wr32(hw, hw->aq.arq.len, 0); in iavf_shutdown_arq()
484 wr32(hw, hw->aq.arq.bal, 0); in iavf_shutdown_arq()
[all …]
/linux/drivers/net/ethernet/intel/ice/
A Dice_ptp_hw.c432 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); in ice_ptp_unlock()
468 wr32(hw, GLTSYN_CMD, cmd_val); in ice_ptp_src_cmd()
499 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); in ice_ptp_tmr_cmd()
525 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); in ice_ptp_init_time()
526 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); in ice_ptp_init_time()
527 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); in ice_ptp_init_time()
560 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); in ice_ptp_write_incval()
561 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); in ice_ptp_write_incval()
616 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); in ice_ptp_adj_clock()
617 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); in ice_ptp_adj_clock()
A Dice_controlq.c276 wr32(hw, ring->head, 0); in ice_cfg_cq_regs()
277 wr32(hw, ring->tail, 0); in ice_cfg_cq_regs()
490 wr32(hw, cq->sq.head, 0); in ice_shutdown_sq()
491 wr32(hw, cq->sq.tail, 0); in ice_shutdown_sq()
492 wr32(hw, cq->sq.len, 0); in ice_shutdown_sq()
493 wr32(hw, cq->sq.bal, 0); in ice_shutdown_sq()
494 wr32(hw, cq->sq.bah, 0); in ice_shutdown_sq()
557 wr32(hw, cq->rq.head, 0); in ice_shutdown_rq()
559 wr32(hw, cq->rq.len, 0); in ice_shutdown_rq()
560 wr32(hw, cq->rq.bal, 0); in ice_shutdown_rq()
[all …]
A Dice_ptp.c283 wr32(&pf->hw, PFINT_OICR_ENA, val); in ice_set_tx_tstamp()
825 wr32(hw, PFINT_OICR_ENA, irq_reg); in ice_ptp_cfg_extts()
827 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg); in ice_ptp_cfg_extts()
853 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0); in ice_ptp_cfg_clkout()
859 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0); in ice_ptp_cfg_clkout()
860 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0); in ice_ptp_cfg_clkout()
861 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0); in ice_ptp_cfg_clkout()
865 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val); in ice_ptp_cfg_clkout()
916 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val); in ice_ptp_cfg_clkout()
922 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val); in ice_ptp_cfg_clkout()
[all …]
/linux/drivers/infiniband/hw/irdma/
A Di40iw_hw.c116 wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val); in i40iw_config_ceq()
120 wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val); in i40iw_config_ceq()
127 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val); in i40iw_config_ceq()
142 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), val); in i40iw_ena_irq()
152 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), 0); in i40iw_disable_irq()

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