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Searched refs:writel_bits_relaxed (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/meson/
A Dmeson_viu.c105 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_g12a_osd1_matrix()
149 writel_bits_relaxed(3 << 30, m[21] << 30, in meson_viu_set_osd_matrix()
151 writel_bits_relaxed(7 << 16, m[22] << 16, in meson_viu_set_osd_matrix()
157 writel_bits_relaxed(BIT(1), 0, in meson_viu_set_osd_matrix()
221 writel_bits_relaxed(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
224 writel_bits_relaxed(0x7 << 29, 0, in meson_viu_set_osd_lut()
248 writel_bits_relaxed(7 << 27, 7 << 27, in meson_viu_set_osd_lut()
251 writel_bits_relaxed(7 << 27, 0, in meson_viu_set_osd_lut()
254 writel_bits_relaxed(BIT(31), BIT(31), in meson_viu_set_osd_lut()
328 writel_bits_relaxed(VIU_SW_RESET_OSD1, 0, in meson_viu_osd1_reset()
[all …]
A Dmeson_vpp.c97 writel_bits_relaxed(0xff << 16, 0xff << 16, in meson_vpp_init()
111 writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, in meson_vpp_init()
118 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, in meson_vpp_init()
122 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, in meson_vpp_init()
126 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | in meson_vpp_init()
A Dmeson_rdma.c65 writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 | in meson_rdma_setup()
73 writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1, in meson_rdma_stop()
78 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_stop()
129 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_flush()
A Dmeson_crtc.c142 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, in meson_crtc_atomic_enable()
190 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND | in meson_crtc_atomic_disable()
245 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, in meson_crtc_enable_osd1()
254 writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, in meson_crtc_g12a_enable_osd1_afbc()
262 writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, in meson_crtc_g12a_enable_osd1_afbc()
265 writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN, in meson_crtc_g12a_enable_osd1_afbc()
283 writel_bits_relaxed(3 << 8, 3 << 8, in meson_g12a_crtc_enable_osd1()
289 writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | in meson_crtc_enable_vd1()
295 writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1, in meson_crtc_enable_vd1()
A Dmeson_dw_hdmi.c514 writel_bits_relaxed(0x3, 0, in dw_hdmi_phy_init()
516 writel_bits_relaxed(0xf << 8, 0, in dw_hdmi_phy_init()
526 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), in dw_hdmi_phy_init()
531 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, in dw_hdmi_phy_init()
534 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, in dw_hdmi_phy_init()
770 writel_bits_relaxed(0x3, 0, in meson_venc_hdmi_encoder_disable()
918 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_init()
920 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_init()
A Dmeson_osd_afbcd.c107 writel_bits_relaxed(OSD1_AFBCD_DEC_ENABLE, 0, in meson_gxm_afbcd_disable()
283 writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET, in meson_g12a_afbcd_init()
323 writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0, in meson_g12a_afbcd_disable()
A Dmeson_plane.c411 writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, in meson_plane_atomic_disable()
414 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, in meson_plane_atomic_disable()
A Dmeson_venc_cvbs.c185 writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, in meson_venc_cvbs_encoder_enable()
A Dmeson_venc.c1043 writel_bits_relaxed(0xff, 0xff, in meson_venc_hdmi_mode_set()
1398 writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH, in meson_venc_hdmi_mode_set()
1779 writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | in meson_venc_init()
A Dmeson_overlay.c741 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, in meson_overlay_atomic_disable()
A Dmeson_registers.h14 #define writel_bits_relaxed(mask, val, addr) \ macro
/linux/drivers/spi/
A Dspi-meson-spicc.c141 #define writel_bits_relaxed(mask, val, addr) \ macro
260 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, in meson_spicc_setup_burst()
273 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
291 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
366 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, in meson_spicc_reset_fifo()
370 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, in meson_spicc_reset_fifo()
377 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, in meson_spicc_reset_fifo()
411 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
471 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); in meson_spicc_prepare_message()
/linux/drivers/media/cec/platform/meson/
A Dao-cec.c228 #define writel_bits_relaxed(mask, val, addr) \ macro
309 writel_bits_relaxed(cfg, enable ? cfg : 0, in meson_ao_cec_irq_setup()
550 writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET, in meson_ao_cec_adap_enable()
557 writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK, in meson_ao_cec_adap_enable()
565 writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0, in meson_ao_cec_adap_enable()

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