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Searched refs:writeq (Results 1 – 25 of 195) sorted by relevance

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/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
A Dmlxbf_gige_rx.c21 writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER + in mlxbf_gige_set_mac_rx_filter()
27 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_set_mac_rx_filter()
49 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_promisc()
67 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_disable_promisc()
137 writeq(data, priv->base + MLXBF_GIGE_RX); in mlxbf_gige_rx_init()
140 writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN, in mlxbf_gige_rx_init()
142 writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN, in mlxbf_gige_rx_init()
155 writeq(data, priv->base + MLXBF_GIGE_RX_DMA); in mlxbf_gige_rx_init()
157 writeq(ilog2(priv->rx_q_entries), in mlxbf_gige_rx_init()
189 writeq(data, priv->base + MLXBF_GIGE_RX_DMA); in mlxbf_gige_rx_deinit()
[all …]
A Dmlxbf_gige_tx.c31 writeq(priv->tx_wqe_base_dma, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_init()
43 writeq(priv->tx_cc_dma, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_init()
45 writeq(ilog2(priv->tx_q_entries), in mlxbf_gige_tx_init()
88 writeq(0, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_deinit()
89 writeq(0, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_deinit()
267 writeq(priv->tx_pi, priv->base + MLXBF_GIGE_TX_PRODUCER_INDEX); in mlxbf_gige_start_xmit()
A Dmlxbf_gige_main.c114 writeq(control, priv->base + MLXBF_GIGE_CONTROL); in mlxbf_gige_clean_port()
126 writeq(control, priv->base + MLXBF_GIGE_CONTROL); in mlxbf_gige_clean_port()
177 writeq(int_en, priv->base + MLXBF_GIGE_INT_EN); in mlxbf_gige_open()
193 writeq(0, priv->base + MLXBF_GIGE_INT_EN); in mlxbf_gige_stop()
302 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_probe()
415 writeq(0, priv->base + MLXBF_GIGE_INT_EN); in mlxbf_gige_shutdown()
/linux/drivers/infiniband/hw/hfi1/
A Dpio_copy.c38 writeq(pbc, dest); in pio_copy()
51 writeq(*(u64 *)from, dest); in pio_copy()
67 writeq(*(u64 *)from, dest); in pio_copy()
86 writeq(*(u64 *)from, dest); in pio_copy()
97 writeq(*(u64 *)from, dest); in pio_copy()
110 writeq(val.val64, dest); in pio_copy()
118 writeq(0, dest); in pio_copy()
224 writeq(temp, dest); in merge_write8()
233 writeq(carry.val64, dest); in carry8_write8()
269 writeq(pbc, dest); in seg_pio_copy_start()
[all …]
/linux/drivers/net/ethernet/neterion/
A Ds2io.c1212 writeq(val64, &bar0->sw_reset); in init_nic()
1219 writeq(val64, &bar0->sw_reset); in init_nic()
1337 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1745 writeq(val64, &bar0->mac_cfg); in init_nic()
1847 writeq(temp64, addr); in do_s2io_write_bits()
2241 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2247 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
3419 writeq(val64, &bar0->sw_reset); in s2io_reset()
3779 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
4344 writeq(val64, addr); in do_s2io_chk_alarm_bit()
[all …]
/linux/drivers/fpga/
A Ddfl-fme-error.c73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); in pcie0_errors_store()
77 writeq(v, base + PCIE0_ERROR); in pcie0_errors_store()
81 writeq(0ULL, base + PCIE0_ERROR_MASK); in pcie0_errors_store()
118 writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); in pcie1_errors_store()
122 writeq(v, base + PCIE1_ERROR); in pcie1_errors_store()
126 writeq(0ULL, base + PCIE1_ERROR_MASK); in pcie1_errors_store()
194 writeq(v, base + RAS_ERROR_INJECT); in inject_errors_store()
232 writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); in fme_errors_store()
236 writeq(v, base + FME_ERROR); in fme_errors_store()
241 writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR, in fme_errors_store()
[all …]
A Ddfl-fme-mgr.c102 writeq(pr_error, fme_pr + FME_PR_ERR); in fme_mgr_pr_error_handle()
125 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
136 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
160 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
178 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write()
211 writeq(pr_data, fme_pr + FME_PR_DATA); in fme_mgr_write()
230 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_complete()
/linux/drivers/gpio/
A Dgpio-mlxbf.c114 writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD); in mlxbf_gpio_resume()
115 writeq(gs->csave_regs.pad_control[0], in mlxbf_gpio_resume()
117 writeq(gs->csave_regs.pad_control[1], in mlxbf_gpio_resume()
119 writeq(gs->csave_regs.pad_control[2], in mlxbf_gpio_resume()
121 writeq(gs->csave_regs.pad_control[3], in mlxbf_gpio_resume()
123 writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I); in mlxbf_gpio_resume()
124 writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O); in mlxbf_gpio_resume()
A Dgpio-thunderx.c114 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
130 writeq(BIT_ULL(bank_bit), reg); in thunderx_gpio_set()
152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
240 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
284 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
285 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); in thunderx_gpio_set_multiple()
294 writeq(GPIO_INTR_INTR, in thunderx_gpio_irq_ack()
303 writeq(GPIO_INTR_ENA_W1C, in thunderx_gpio_irq_mask()
312 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, in thunderx_gpio_irq_mask_ack()
321 writeq(GPIO_INTR_ENA_W1S, in thunderx_gpio_irq_unmask()
[all …]
/linux/drivers/mmc/host/
A Dcavium.c212 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
215 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
267 writeq(wdog, slot->host->base + MIO_EMM_WDOG(host)); in cvm_mmc_reset_bus()
293 writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host)); in cvm_mmc_switch_to()
432 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cleanup_dma()
449 writeq(emm_int, host->base + MIO_EMM_INT(host)); in cvm_mmc_interrupt()
697 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cvm_mmc_dma_request()
742 writeq(dat, host->base + MIO_EMM_BUF_DAT(host)); in do_write_request()
805 writeq(0, host->base + MIO_EMM_STS_MASK(host)); in cvm_mmc_request()
819 writeq(emm_cmd, host->base + MIO_EMM_CMD(host)); in cvm_mmc_request()
[all …]
A Dcavium-thunderx.c32 writeq(val, host->base + MIO_EMM_INT(host)); in thunder_mmc_int_enable()
33 writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); in thunder_mmc_int_enable()
122 writeq(127, host->base + MIO_EMM_INT_EN(host)); in thunder_mmc_probe()
123 writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host)); in thunder_mmc_probe()
125 writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host)); in thunder_mmc_probe()
180 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
A Dcavium-octeon.c94 writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL); in octeon_mmc_acquire_bus()
110 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_int_enable()
112 writeq(val, host->base + MIO_EMM_INT_EN(host)); in octeon_mmc_int_enable()
233 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_probe()
308 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in octeon_mmc_remove()
/linux/sound/core/seq/oss/
A Dseq_oss_ioctl.c84 if (! is_write_mode(dp->file_mode) || dp->writeq == NULL) in snd_seq_oss_ioctl()
86 while (snd_seq_oss_writeq_sync(dp->writeq)) in snd_seq_oss_ioctl()
107 if (! is_write_mode(dp->file_mode) || dp->writeq == NULL) in snd_seq_oss_ioctl()
109 return put_user(snd_seq_oss_writeq_get_free_size(dp->writeq), p) ? -EFAULT : 0; in snd_seq_oss_ioctl()
154 if (val >= dp->writeq->maxlen) in snd_seq_oss_ioctl()
155 val = dp->writeq->maxlen - 1; in snd_seq_oss_ioctl()
156 snd_seq_oss_writeq_set_output(dp->writeq, val); in snd_seq_oss_ioctl()
/linux/drivers/net/ethernet/cavium/liquidio/
A Docteon_mailbox.c80 writeq(OCTEON_PFVFERR, in octeon_mbox_read()
115 writeq(OCTEON_PFVFACK, mbox->mbox_read_reg); in octeon_mbox_read()
172 writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg); in octeon_mbox_write()
184 writeq(mbox_cmd->data[i], mbox->mbox_write_reg); in octeon_mbox_write()
193 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_write()
306 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
316 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
325 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
341 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
371 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_cancel()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
A Dptp.c110 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
161 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
164 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_HI_INCR); in ptp_start()
165 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_LO_INCR); in ptp_start()
169 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_start()
181 writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_set_thresh()
245 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_remove()
/linux/drivers/net/ethernet/neterion/vxge/
A Dvxge-traffic.c653 writeq( in __vxge_hw_vpath_alarm_process()
674 writeq( in __vxge_hw_vpath_alarm_process()
683 writeq(VXGE_HW_INTR_MASK_ALL, in __vxge_hw_vpath_alarm_process()
738 writeq(VXGE_HW_INTR_MASK_ALL, in __vxge_hw_vpath_alarm_process()
783 writeq(VXGE_HW_INTR_MASK_ALL, in __vxge_hw_vpath_alarm_process()
834 writeq(VXGE_HW_INTR_MASK_ALL, in __vxge_hw_vpath_alarm_process()
1390 writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr); in __vxge_hw_non_offload_db_post()
1992 writeq(val64, &vpath->vp_reg->rxmac_vcfg0); in vxge_hw_vpath_promisc_enable()
2028 writeq(val64, &vpath->vp_reg->rxmac_vcfg0); in vxge_hw_vpath_promisc_disable()
2058 writeq(val64, &vpath->vp_reg->rxmac_vcfg0); in vxge_hw_vpath_bcast_enable()
[all …]
A Dvxge-config.c40 writeq(val64, &vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()
4077 writeq(val64, &vp_reg->prc_cfg1); in __vxge_hw_vpath_prc_configure()
4106 writeq(val64, &vp_reg->prc_cfg7); in __vxge_hw_vpath_prc_configure()
4108 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( in __vxge_hw_vpath_prc_configure()
4124 writeq(val64, &vp_reg->prc_cfg4); in __vxge_hw_vpath_prc_configure()
4284 writeq(0, &vp_reg->tim_dest_addr); in __vxge_hw_vpath_tim_configure()
4285 writeq(0, &vp_reg->tim_vpath_map); in __vxge_hw_vpath_tim_configure()
4286 writeq(0, &vp_reg->tim_bitmap); in __vxge_hw_vpath_tim_configure()
4287 writeq(0, &vp_reg->tim_remap); in __vxge_hw_vpath_tim_configure()
4296 writeq(val64, &vp_reg->tim_pci_cfg); in __vxge_hw_vpath_tim_configure()
[all …]
/linux/drivers/crypto/marvell/octeontx/
A Dotx_cptpf_mbox.c78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
120 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_qlen_for_vf()
132 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_vq_priority()
162 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q)); in otx_cpt_bind_vq_to_grp()
A Dotx_cptvf_main.c354 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
363 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
372 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
381 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
398 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_timewait()
447 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_dovf_intr()
457 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_irde_intr()
467 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_nwrp_intr()
477 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_mbox_intr()
487 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_swerr_intr()
[all …]
/linux/drivers/spi/
A Dspi-cavium.c66 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p)); in octeon_spi_do_transfer()
78 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
85 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
102 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
113 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
/linux/drivers/edac/
A Dthunderx_edac.c281 writeq(val, pdata->regs + _reg); \
315 writeq(val, lmc->regs + LMC_INT_W1S); in thunderx_lmc_inject_int_write()
553 writeq(0, lmc->regs + LMC_CHAR_MASK0); in thunderx_lmc_err_isr()
554 writeq(0, lmc->regs + LMC_CHAR_MASK2); in thunderx_lmc_err_isr()
568 writeq(ctx->reg_int, lmc->regs + LMC_INT); in thunderx_lmc_err_isr()
778 writeq(lmc_int, lmc->regs + LMC_INT); in thunderx_lmc_probe()
1445 writeq(OCX_LNE_INT_ENA_ALL, in thunderx_ocx_probe()
1449 writeq(reg, ocx->regs + OCX_LNE_INT(i)); in thunderx_ocx_probe()
1457 writeq(OCX_COM_LINKX_INT_ENA_ALL, in thunderx_ocx_probe()
1462 writeq(reg, ocx->regs + OCX_COM_INT); in thunderx_ocx_probe()
[all …]
/linux/drivers/char/hw_random/
A Dcavium-rng.c45 writeq(THUNDERX_RNM_RNG_EN | THUNDERX_RNM_ENT_EN, in cavium_rng_probe()
54 writeq(0, rng->control_status); in cavium_rng_probe()
75 writeq(0, rng->control_status); in cavium_rng_remove()
/linux/sound/mips/
A Dsgio2audio.c109 writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | in read_ad1843_reg()
132 writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | in write_ad1843_reg()
446 writeq(CHANNEL_CONTROL_RESET, &mace->perif.audio.chan[ch].control); in snd_sgio2audio_dma_start()
448 writeq(0, &mace->perif.audio.chan[ch].control); in snd_sgio2audio_dma_start()
455 writeq(CHANNEL_DMA_ENABLE | CHANNEL_INT_THRESHOLD_50, in snd_sgio2audio_dma_start()
464 writeq(0, &mace->perif.audio.chan[chan->idx].control); in snd_sgio2audio_dma_stop()
759 writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); in snd_sgio2audio_free()
761 writeq(0, &mace->perif.audio.control); in snd_sgio2audio_free()
839 writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); in snd_sgio2audio_create()
841 writeq(0, &mace->perif.audio.control); in snd_sgio2audio_create()
[all …]
/linux/drivers/net/ethernet/cavium/common/
A Dcavium_ptp.c129 writeq(comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_adjfine()
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
280 writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_probe()
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
323 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
/linux/drivers/misc/ocxl/
A Dmmio.c100 writeq(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write64()
163 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_set64()
226 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
230 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()

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