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Searched refs:ARRAY_SIZE (Results 1 – 25 of 65) sorted by relevance

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/optee_os/core/drivers/
A Dstpmic1.c435 .voltage_table_size = ARRAY_SIZE(buck1_voltage_table),
447 .voltage_table_size = ARRAY_SIZE(buck2_voltage_table),
459 .voltage_table_size = ARRAY_SIZE(buck3_voltage_table),
483 .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table),
493 .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table),
503 .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table),
513 .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table),
523 .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table),
533 .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table),
577 for (i = 0; i < ARRAY_SIZE(regulators_table); i++) in get_regulator_data()
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A Dimx_i2c.c72 uint32_t i2c[ARRAY_SIZE(i2c_bus)];
73 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)];
89 } i2c[ARRAY_SIZE(i2c_bus)];
171 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; in i2c_set_prescaler()
353 if (bid >= ARRAY_SIZE(i2c_bus)) in imx_i2c_read()
376 if (bid >= ARRAY_SIZE(i2c_bus)) in imx_i2c_write()
397 if (bid >= ARRAY_SIZE(i2c_bus)) in imx_i2c_probe()
418 if (bid >= ARRAY_SIZE(i2c_bus)) in imx_i2c_init()
470 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { in i2c_mapped()
497 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) { in i2c_map_controller()
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/optee_os/core/drivers/clk/sam/
A Dsama5d2_clk.c20 #define PARENT_SIZE ARRAY_SIZE(sama5d2_systemck)
42 .num_output = ARRAY_SIZE(plla_outputs),
362 ARRAY_SIZE(sama5d2_systemck), in pmc_setup()
363 ARRAY_SIZE(sama5d2_perick) + in pmc_setup()
364 ARRAY_SIZE(sama5d2_peri32ck), in pmc_setup()
365 ARRAY_SIZE(sama5d2_gck), in pmc_setup()
366 ARRAY_SIZE(sama5d2_progck)); in pmc_setup()
487 for (i = 0; i < ARRAY_SIZE(sama5d2_progck); i++) { in pmc_setup()
510 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) { in pmc_setup()
523 for (i = 0; i < ARRAY_SIZE(sama5d2_perick); i++) { in pmc_setup()
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/optee_os/ta/pkcs11/src/
A Dpkcs11_attributes.c495 ARRAY_SIZE(any_object_boolprops)); in create_storage_attributes()
500 ARRAY_SIZE(any_object_opt_or_null)); in create_storage_attributes()
524 ARRAY_SIZE(any_key_boolprops)); in create_genkey_attributes()
529 ARRAY_SIZE(any_key_opt_or_null)); in create_genkey_attributes()
534 ARRAY_SIZE(any_key_optional)); in create_genkey_attributes()
569 ARRAY_SIZE(symm_key_boolprops)); in create_symm_key_attributes()
574 ARRAY_SIZE(symm_key_opt_or_null)); in create_symm_key_attributes()
579 ARRAY_SIZE(symm_key_optional)); in create_symm_key_attributes()
596 ARRAY_SIZE(raw_data_opt_or_null)); in create_data_attributes()
745 ARRAY_SIZE(public_key_opt_or_null)); in create_pub_key_attributes()
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A Dtoken_capabilities.c151 for (n = 0; n < ARRAY_SIZE(pkcs11_modes); n++) in mechanism_string_id()
166 for (n = 0; n < ARRAY_SIZE(pkcs11_modes); n++) in mechanism_is_valid()
183 for (n = 0; n < ARRAY_SIZE(pkcs11_modes); n++) { in mechanism_flags_complies_pkcs11()
202 for (n = 0; n < ARRAY_SIZE(pkcs11_modes); n++) in mechanism_is_one_shot_only()
292 for (n = 0; n < ARRAY_SIZE(token_mechanism); n++) in tee_malloc_mechanism_list()
305 for (n = 0; n < ARRAY_SIZE(token_mechanism); n++) { in tee_malloc_mechanism_list()
320 for (n = 0; n < ARRAY_SIZE(token_mechanism); n++) { in mechanism_supported_flags()
A Dpkcs11_helpers.c121 id2str(id, table, ARRAY_SIZE(table), prefix)
409 for (n = 0; n < ARRAY_SIZE(attr_ids); n++) in valid_pkcs11_attribute_id()
537 for (pos = 0; pos < ARRAY_SIZE(bpa); pos++) in pkcs11_attr2boolprop_shift()
745 for (n = 0; n < ARRAY_SIZE(attr_ids); n++) { in id2str_attr()
/optee_os/core/arch/arm/plat-stm32mp1/
A Dscmi_server.c181 .clock_count = ARRAY_SIZE(stm32_scmi0_clock),
183 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain),
185 .voltd_count = ARRAY_SIZE(scmi0_voltage_domain),
193 .clock_count = ARRAY_SIZE(stm32_scmi1_clock),
199 assert(channel_id < ARRAY_SIZE(scmi_channel)); in find_resource()
206 const size_t max_id = ARRAY_SIZE(scmi_channel); in plat_scmi_get_channel()
219 const size_t channel_count = ARRAY_SIZE(scmi_channel); in plat_scmi_protocol_count_paranoid()
265 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; in plat_scmi_protocol_count()
275 (ARRAY_SIZE(plat_protocol_list) - 1)); in plat_scmi_protocol_list()
817 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { in stm32mp1_init_scmi_server()
/optee_os/core/arch/arm/plat-imx/pm/
A Dpm-imx7.c82 .ddrc_num = ARRAY_SIZE(imx7d_ddrc_ddr3_setting),
84 .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_ddr3_setting),
109 for (i = 0; i < ARRAY_SIZE(phys_addr); i++) { in pm_imx7_iram_tbl_init()
/optee_os/core/drivers/clk/
A Dclk-stm32mp15.c164 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) in clock_id2parent_id()
321 .nb_parent = ARRAY_SIZE(_parent) \
340 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
577 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { in osc_frequency()
1221 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { in enable_static_secure_clocks()
1297 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) +
1298 ARRAY_SIZE(stm32mp1_clk_on)];
1334 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) in clock_id_to_gate_index()
1345 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) in clock_id_to_always_on_index()
1429 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) in clk_op_get_name()
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/optee_os/core/drivers/scmi-msg/
A Dbase.c182 return message_id < ARRAY_SIZE(scmi_base_handler_table) && in message_id_is_supported()
188 const size_t array_size = ARRAY_SIZE(scmi_base_handler_table); in scmi_msg_get_base_handler()
A Dreset_domain.c177 return message_id < ARRAY_SIZE(scmi_rd_handler_table) && in message_id_is_supported()
183 const size_t array_size = ARRAY_SIZE(scmi_rd_handler_table); in scmi_msg_get_rd_handler()
A Dvoltage_domain.c210 ret_nb = MIN(ARRAY_SIZE(plat_levels), in scmi_voltd_describe_levels()
392 return id < ARRAY_SIZE(handler_array) && handler_array[id]; in message_id_is_supported()
397 const size_t array_size = ARRAY_SIZE(handler_array); in scmi_msg_get_voltd_handler()
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_ctrl.c44 caam_pwr_add_backup(baseaddr, ctrl_backup, ARRAY_SIZE(ctrl_backup)); in caam_hal_ctrl_init()
A Dhal_jr.c92 ARRAY_SIZE(jrcfg_backup)); in caam_hal_jr_prepare_backup()
/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c179 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { in write_slcr()
200 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { in read_slcr()
/optee_os/core/drivers/crypto/crypto_api/oid/
A Dhash_oid.c36 if (main_alg < ARRAY_SIZE(drvcrypt_hash_oid)) in drvcrypt_get_alg_hash_oid()
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pmic.c228 for (i = 0; i < ARRAY_SIZE(regu_lp_state); i++) in regu_lp_state2idx()
382 for (n = 0; n < ARRAY_SIZE(nsec_access_regu_name); n++) in stm32mp_nsec_can_access_pmic_regu()
396 for (n = 0; n < ARRAY_SIZE(nsec_access_regu_name); n++) { in register_nsec_regu()
448 for (n = 0; n < ARRAY_SIZE(regu_lp_state); n++) in parse_regulator_fdt_nodes()
/optee_os/out/arm/export-ta_arm32/host_include/
A Dutil.h43 #ifndef ARRAY_SIZE
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
/optee_os/out/arm/export-ta_arm64/include/
A Dutil.h43 #ifndef ARRAY_SIZE
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
/optee_os/out/arm/export-ta_arm64/host_include/
A Dutil.h43 #ifndef ARRAY_SIZE
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
/optee_os/lib/libutils/ext/include/
A Dutil.h43 #ifndef ARRAY_SIZE
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
/optee_os/out/arm/export-ta_arm32/include/
A Dutil.h43 #ifndef ARRAY_SIZE
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
/optee_os/core/arch/arm/plat-vexpress/
A Dvendor_props.c70 .len = ARRAY_SIZE(vendor_propset_array_tee),
/optee_os/core/arch/arm/kernel/
A Drpc_io_i2c.c45 res = thread_rpc_cmd(OPTEE_RPC_CMD_I2C_TRANSFER, ARRAY_SIZE(p), p); in rpc_io_i2c_transfer()
/optee_os/core/arch/arm/mm/
A Dpgt_cache.c85 for (n = 0; n < ARRAY_SIZE(pgt_parents); n++) { in pgt_init()
111 for (n = 0; n < ARRAY_SIZE(pgt_tables); n++) { in pgt_init()
144 for (n = 0; n < ARRAY_SIZE(pgt_parents); n++) { in pop_from_free_list()

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