1 /* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
2 /*
3  * Copyright (C) 2005 Ivan Kokshaysky
4  * Copyright (C) SAN People
5  *
6  * Power Management Controller (PMC) - System peripherals registers.
7  * Based on AT91RM9200 datasheet revision E.
8  */
9 
10 #ifndef DRIVERS_CLK_SAM_AT91_PM_H
11 #define DRIVERS_CLK_SAM_AT91_PM_H
12 
13 #include <util.h>
14 
15 #define AT91_PMC_V1				(1)
16 #define AT91_PMC_V2				(2)
17 
18 #define	AT91_PMC_SCER				0x00
19 #define	AT91_PMC_SCDR				0x04
20 
21 #define	AT91_PMC_SCSR				0x08
22 #define	  AT91_PMC_PCK				BIT(0)
23 #define	  AT91RM9200_PMC_UDP			BIT(1)
24 #define	  AT91RM9200_PMC_MCKUDP			BIT(2)
25 #define	  AT91RM9200_PMC_UHP			BIT(4)
26 #define	  AT91SAM926x_PMC_UHP			BIT(6)
27 #define	  AT91SAM926x_PMC_UDP			BIT(7)
28 #define	  AT91_PMC_PCK0				BIT(8)
29 #define	  AT91_PMC_PCK1				BIT(9)
30 #define	  AT91_PMC_PCK2				BIT(10)
31 #define	  AT91_PMC_PCK3				BIT(11)
32 #define	  AT91_PMC_PCK4				BIT(12)
33 #define	  AT91_PMC_HCK0				BIT(16)
34 #define	  AT91_PMC_HCK1				BIT(17)
35 
36 #define AT91_PMC_PLL_CTRL0			0x0C
37 #define	  AT91_PMC_PLL_CTRL0_ENPLL		BIT(28)
38 #define	  AT91_PMC_PLL_CTRL0_ENPLLCK		BIT(29)
39 #define	  AT91_PMC_PLL_CTRL0_ENLOCK		BIT(31)
40 
41 #define AT91_PMC_PLL_CTRL1			0x10
42 
43 #define	AT91_PMC_PCER				0x10
44 #define	AT91_PMC_PCDR				0x14
45 #define	AT91_PMC_PCSR				0x18
46 
47 #define AT91_PMC_PLL_ACR			0x18
48 #define	  AT91_PMC_PLL_ACR_DEFAULT_UPLL		0x12020010UL
49 #define	  AT91_PMC_PLL_ACR_DEFAULT_PLLA		0x00020010UL
50 #define	  AT91_PMC_PLL_ACR_UTMIVR		BIT(12)
51 #define	  AT91_PMC_PLL_ACR_UTMIBG		BIT(13)
52 
53 #define	AT91_CKGR_UCKR				0x1C
54 #define	  AT91_PMC_UPLLEN			BIT(16)
55 #define	  AT91_PMC_UPLLCOUNT			(0xf << 20)
56 #define	  AT91_PMC_BIASEN			BIT(24)
57 #define	  AT91_PMC_BIASCOUNT			(0xf << 28)
58 
59 #define AT91_PMC_PLL_UPDT			0x1C
60 #define	  AT91_PMC_PLL_UPDT_UPDATE		BIT(8)
61 #define	  AT91_PMC_PLL_UPDT_ID			BIT(0)
62 #define	  AT91_PMC_PLL_UPDT_ID_MSK		(0xf)
63 #define	  AT91_PMC_PLL_UPDT_STUPTIM		(0xff << 16)
64 
65 #define	AT91_CKGR_MOR				0x20
66 #define	  AT91_PMC_MOSCEN			BIT(0)
67 #define	  AT91_PMC_OSCBYPASS			BIT(1)
68 #define	  AT91_PMC_WAITMODE			BIT(2)
69 #define	  AT91_PMC_MOSCRCEN			BIT(3)
70 #define	  AT91_PMC_OSCOUNT			(0xff << 8)
71 #define	  AT91_PMC_KEY_MASK			(0xff << 16)
72 #define	  AT91_PMC_KEY				(0x37 << 16)
73 #define	  AT91_PMC_MOSCSEL			BIT(24)
74 #define	  AT91_PMC_CFDEN			BIT(25)
75 
76 #define	AT91_CKGR_MCFR				0x24
77 #define	  AT91_PMC_MAINF			(0xffff << 0)
78 #define	  AT91_PMC_MAINRDY			BIT(16)
79 
80 #define	AT91_CKGR_PLLAR				0x28
81 #define	AT91_CKGR_PLLBR				0x2c
82 #define	  AT91_PMC_DIV				(0xff << 0)
83 #define	  AT91_PMC_PLLCOUNT			(0x3f << 8)
84 #define	  AT91_PMC_OUT				(3 << 14)
85 #define	  AT91_PMC_MUL				(0x7ff << 16)
86 #define	  AT91_PMC_MUL_GET(n)			((n) >> 16 & 0x7ff)
87 #define	  AT91_PMC3_MUL				(0x7f << 18)
88 #define	  AT91_PMC3_MUL_GET(n)			((n) >> 18 & 0x7f)
89 #define	  AT91_PMC_USBDIV			(3 << 28)
90 #define     AT91_PMC_USBDIV_1			(0 << 28)
91 #define     AT91_PMC_USBDIV_2			BIT(28)
92 #define     AT91_PMC_USBDIV_4			(2 << 28)
93 #define	  AT91_PMC_USB96M			BIT(28)
94 
95 #define AT91_PMC_CPU_CKR			0x28
96 
97 #define	AT91_PMC_MCKR				0x30
98 #define	  AT91_PMC_CSS				(3 << 0)
99 #define     AT91_PMC_CSS_SLOW			(0 << 0)
100 #define     AT91_PMC_CSS_MAIN			BIT(0)
101 #define     AT91_PMC_CSS_PLLA			(2 << 0)
102 #define     AT91_PMC_CSS_PLLB			(3 << 0)
103 #define     AT91_PMC_CSS_UPLL			(3 << 0)
104 #define	  PMC_PRES_OFFSET			2
105 #define	  AT91_PMC_PRES				(7 << PMC_PRES_OFFSET)
106 #define     AT91_PMC_PRES_1			(0 << PMC_PRES_OFFSET)
107 #define     AT91_PMC_PRES_2			BIT(PMC_PRES_OFFSET)
108 #define     AT91_PMC_PRES_4			(2 << PMC_PRES_OFFSET)
109 #define     AT91_PMC_PRES_8			(3 << PMC_PRES_OFFSET)
110 #define     AT91_PMC_PRES_16			(4 << PMC_PRES_OFFSET)
111 #define     AT91_PMC_PRES_32			(5 << PMC_PRES_OFFSET)
112 #define     AT91_PMC_PRES_64			(6 << PMC_PRES_OFFSET)
113 #define	  PMC_ALT_PRES_OFFSET			4
114 #define	  AT91_PMC_ALT_PRES			(7 << PMC_ALT_PRES_OFFSET)
115 #define     AT91_PMC_ALT_PRES_1			(0 << PMC_ALT_PRES_OFFSET)
116 #define     AT91_PMC_ALT_PRES_2			BIT(PMC_ALT_PRES_OFFSET)
117 #define     AT91_PMC_ALT_PRES_4			(2 << PMC_ALT_PRES_OFFSET)
118 #define     AT91_PMC_ALT_PRES_8			(3 << PMC_ALT_PRES_OFFSET)
119 #define     AT91_PMC_ALT_PRES_16		(4 << PMC_ALT_PRES_OFFSET)
120 #define     AT91_PMC_ALT_PRES_32		(5 << PMC_ALT_PRES_OFFSET)
121 #define     AT91_PMC_ALT_PRES_64		(6 << PMC_ALT_PRES_OFFSET)
122 #define	  AT91_PMC_MDIV				(3 << 8)
123 #define     AT91RM9200_PMC_MDIV_1		(0 << 8)
124 #define     AT91RM9200_PMC_MDIV_2		BIT(8)
125 #define     AT91RM9200_PMC_MDIV_3		(2 << 8)
126 #define     AT91RM9200_PMC_MDIV_4		(3 << 8)
127 #define     AT91SAM9_PMC_MDIV_1			(0 << 8)
128 #define     AT91SAM9_PMC_MDIV_2			BIT(8)
129 #define     AT91SAM9_PMC_MDIV_4			(2 << 8)
130 #define     AT91SAM9_PMC_MDIV_6			(3 << 8)
131 #define     AT91SAM9_PMC_MDIV_3			(3 << 8)
132 #define	  AT91_PMC_PDIV				BIT(12)
133 #define     AT91_PMC_PDIV_1			(0 << 12)
134 #define     AT91_PMC_PDIV_2			BIT(12)
135 #define	  AT91_PMC_PLLADIV2			BIT(12)
136 #define     AT91_PMC_PLLADIV2_OFF		(0 << 12)
137 #define     AT91_PMC_PLLADIV2_ON		BIT(12)
138 #define	  AT91_PMC_H32MXDIV	BIT(24)
139 
140 #define AT91_PMC_XTALF				0x34
141 
142 #define	AT91_PMC_USB				0x38
143 #define	  AT91_PMC_USBS				(0x1 << 0)
144 #define     AT91_PMC_USBS_PLLA			(0 << 0)
145 #define     AT91_PMC_USBS_UPLL			BIT(0)
146 #define     AT91_PMC_USBS_PLLB			BIT(0)
147 #define	  AT91_PMC_OHCIUSBDIV			(0xF << 8)
148 #define     AT91_PMC_OHCIUSBDIV_1		(0x0 << 8)
149 #define     AT91_PMC_OHCIUSBDIV_2		(0x1 << 8)
150 
151 #define	AT91_PMC_SMD				0x3c
152 #define	  AT91_PMC_SMDS				(0x1 << 0)
153 #define	  AT91_PMC_SMD_DIV			(0x1f << 8)
154 #define	  AT91_PMC_SMDDIV(n)			(((n) << 8) & AT91_PMC_SMD_DIV)
155 
156 #define	AT91_PMC_PCKR(n)			(0x40 + ((n) * 4))
157 #define	  AT91_PMC_ALT_PCKR_CSS			(0x7 << 0)
158 #define     AT91_PMC_CSS_MASTER			(4 << 0)
159 #define	  AT91_PMC_CSSMCK			(0x1 << 8)
160 #define     AT91_PMC_CSSMCK_CSS			(0 << 8)
161 #define     AT91_PMC_CSSMCK_MCK			BIT(8)
162 
163 #define	AT91_PMC_IER				0x60
164 #define	AT91_PMC_IDR				0x64
165 #define	AT91_PMC_SR				0x68
166 #define	  AT91_PMC_MOSCS			BIT(0)
167 #define	  AT91_PMC_LOCKA			BIT(1)
168 #define	  AT91_PMC_LOCKB			BIT(2)
169 #define	  AT91_PMC_MCKRDY			BIT(3)
170 #define	  AT91_PMC_LOCKU			BIT(6)
171 #define	  AT91_PMC_OSCSEL			BIT(7)
172 #define	  AT91_PMC_PCK0RDY			BIT(8)
173 #define	  AT91_PMC_PCK1RDY			BIT(9)
174 #define	  AT91_PMC_PCK2RDY			BIT(10)
175 #define	  AT91_PMC_PCK3RDY			BIT(11)
176 #define	  AT91_PMC_MOSCSELS			BIT(16)
177 #define	  AT91_PMC_MOSCRCS			BIT(17)
178 #define	  AT91_PMC_CFDEV			BIT(18)
179 #define	  AT91_PMC_GCKRDY			BIT(24)
180 #define	  AT91_PMC_MCKXRDY			BIT(26)
181 #define	AT91_PMC_IMR				0x6c
182 
183 #define AT91_PMC_FSMR				0x70
184 #define AT91_PMC_FSTT(n)			BIT(n)
185 #define AT91_PMC_RTTAL				BIT(16)
186 #define AT91_PMC_RTCAL				BIT(17)
187 #define AT91_PMC_USBAL				BIT(18)
188 #define AT91_PMC_SDMMC_CD			BIT(19)
189 #define AT91_PMC_LPM				BIT(20)
190 #define AT91_PMC_RXLP_MCE			BIT(24)
191 #define AT91_PMC_ACC_CE				BIT(25)
192 
193 #define AT91_PMC_FSPR				0x74
194 
195 #define AT91_PMC_FS_INPUT_MASK			0x7ff
196 
197 #define AT91_PMC_PLLICPR			0x80
198 
199 #define AT91_PMC_PROT				0xe4
200 #define	  AT91_PMC_WPEN				(0x1 << 0)
201 #define	  AT91_PMC_WPKEY			(0xffffff << 8)
202 #define	  AT91_PMC_PROTKEY			(0x504d43 << 8)
203 
204 #define AT91_PMC_WPSR				0xe8
205 #define	  AT91_PMC_WPVS				(0x1 << 0)
206 #define	  AT91_PMC_WPVSRC			(0xffff << 8)
207 
208 #define AT91_PMC_PLL_ISR0			0xEC
209 
210 #define AT91_PMC_PCER1				0x100
211 #define AT91_PMC_PCDR1				0x104
212 #define AT91_PMC_PCSR1				0x108
213 
214 #define AT91_PMC_PCR				0x10c
215 #define	  AT91_PMC_PCR_PID_MASK			0x3f
216 #define	  AT91_PMC_PCR_CMD			(0x1 << 12)
217 #define	  AT91_PMC_PCR_GCKDIV_SHIFT		20
218 #define	  AT91_PMC_PCR_GCKDIV_MASK \
219 				GENMASK_32(27, AT91_PMC_PCR_GCKDIV_SHIFT)
220 #define	  AT91_PMC_PCR_EN			(0x1 << 28)
221 #define	  AT91_PMC_PCR_GCKEN			(0x1 << 29)
222 
223 #define AT91_PMC_AUDIO_PLL0			0x14c
224 #define	  AT91_PMC_AUDIO_PLL_PLLEN		BIT(0)
225 #define	  AT91_PMC_AUDIO_PLL_PADEN		BIT(1)
226 #define	  AT91_PMC_AUDIO_PLL_PMCEN		BIT(2)
227 #define	  AT91_PMC_AUDIO_PLL_RESETN		BIT(3)
228 #define	  AT91_PMC_AUDIO_PLL_ND_OFFSET	8
229 #define	  AT91_PMC_AUDIO_PLL_ND_MASK \
230 				(0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
231 #define	  AT91_PMC_AUDIO_PLL_ND(n) \
232 				SHIFT_U32(n, AT91_PMC_AUDIO_PLL_ND_OFFSET)
233 #define	  AT91_PMC_AUDIO_PLL_QDPMC_OFFSET	16
234 #define	  AT91_PMC_AUDIO_PLL_QDPMC_MASK \
235 				(0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
236 #define	  AT91_PMC_AUDIO_PLL_QDPMC(n) \
237 				SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
238 
239 #define AT91_PMC_AUDIO_PLL1			0x150
240 #define	  AT91_PMC_AUDIO_PLL_FRACR_MASK		0x3fffff
241 #define	  AT91_PMC_AUDIO_PLL_QDPAD_OFFSET	24
242 #define	  AT91_PMC_AUDIO_PLL_QDPAD_MASK \
243 				(0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
244 #define	  AT91_PMC_AUDIO_PLL_QDPAD(n) \
245 				SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
246 #define	  AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET \
247 				AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
248 #define	  AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK \
249 				(0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
250 #define	  AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) \
251 			SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
252 #define	  AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET	26
253 #define	  AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX		0x1f
254 #define	  AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK \
255 				(AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << \
256 				AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
257 #define	  AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) \
258 			SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
259 
260 #endif
261