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Searched refs:CFG_TZDRAM_START (Results 1 – 25 of 44) sorted by relevance

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/optee_os/core/arch/arm/plat-mediatek/
A Dconf.mk27 CFG_TZDRAM_START ?= 0xbe000000
38 CFG_TZDRAM_START ?= 0x43200000
40 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
47 CFG_TZDRAM_START ?= 0x4fd00000
49 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
58 CFG_TZDRAM_START ?= 0x4fd00000
60 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
/optee_os/core/arch/arm/include/mm/
A Dgeneric_ram_layout.h141 #ifdef CFG_TZDRAM_START
143 #define TZDRAM_BASE CFG_TZDRAM_START
146 #define TZSRAM_BASE CFG_TZDRAM_START
150 #define TZDRAM_SIZE (CFG_TZDRAM_START + (CFG_TZDRAM_SIZE - \
186 #define TEE_SDP_TEST_MEM_BASE (CFG_TZDRAM_START + (CFG_TZDRAM_SIZE - \
/optee_os/core/arch/arm/plat-vexpress/
A Dconf.mk63 CFG_TZDRAM_START ?= 0x06281000
66 CFG_TZDRAM_START ?= 0x06000000
78 CFG_TZDRAM_START ?= 0xff000000
91 CFG_TZDRAM_START ?= 0x0e100000
118 CFG_TZDRAM_START ?= 0x0e100000
/optee_os/core/arch/arm/plat-marvell/
A Dconf.mk6 $(call force,CFG_TZDRAM_START,0x04400000)
20 $(call force,CFG_TZDRAM_START,0x04400000)
36 $(call force,CFG_TZDRAM_START,0x00001000)
55 $(call force,CFG_TZDRAM_START,0x00001000)
74 $(call force,CFG_TZDRAM_START,0x00001000)
/optee_os/core/arch/arm/plat-totalcompute/
A Dconf.mk33 CFG_TZDRAM_START ?= 0xfd000000
36 CFG_TZDRAM_START ?= 0xfd281000
39 CFG_TZDRAM_START ?= 0xff000000
/optee_os/core/arch/arm/plat-rockchip/
A Dconf.mk17 CFG_TZDRAM_START ?= 0x68400000
34 CFG_TZDRAM_START ?= 0x30000000
50 CFG_TZDRAM_START ?= 0x30000000
A Dplatform.c39 ret = platform_secure_ddr_region(1, CFG_TZDRAM_START, CFG_TZDRAM_SIZE); in platform_init()
/optee_os/core/arch/arm/plat-k3/
A Dconf.mk7 CFG_TZDRAM_START ?= 0x9e800000
9 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
/optee_os/core/arch/arm/plat-stm/
A Dconf.mk41 CFG_TZDRAM_START ?= ($(CFG_DDR_TEETZ_RESERVED_START))
45 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
/optee_os/core/arch/arm/plat-bcm/
A Dconf.mk13 CFG_TZDRAM_START ?= 0x8e000000
15 CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) - $(CFG_SHMEM_SIZE))
/optee_os/core/arch/arm/plat-sunxi/
A Dconf.mk23 CFG_TZDRAM_START ?= 0x5c000000
34 CFG_TZDRAM_START ?= 0x40000000
/optee_os/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c117 CFG_TZDRAM_START + CFG_TZDRAM_SIZE - 1); in plat_primary_init_early()
119 CFG_TZDRAM_START | BIT(0)); in plat_primary_init_early()
A Dconf.mk17 CFG_TZDRAM_START ?= 0x88000000
/optee_os/core/arch/arm/plat-rcar/
A Dlink.mk3 SRECFLAGS ?= --srec-forceS3 --adjust-vma=$(CFG_TZDRAM_START)
A Dconf.mk14 CFG_TZDRAM_START ?= 0x44100000
/optee_os/core/arch/arm/plat-uniphier/
A Dplatform_config.h52 #define CFG_TEE_LOAD_ADDR CFG_TZDRAM_START
/optee_os/core/arch/arm/plat-amlogic/
A Dconf.mk7 CFG_TZDRAM_START ?= 0x05300000
/optee_os/core/arch/arm/plat-synquacer/
A Dconf.mk10 CFG_TZDRAM_START ?= 0xfc000000
/optee_os/core/arch/arm/plat-stm32mp1/
A Dconf.mk46 CFG_TZDRAM_START ?= 0xde000000
55 CFG_TZDRAM_START ?= 0xfe000000
/optee_os/core/arch/arm/plat-imx/drivers/
A Dtzc380.c48 region = tzc_auto_configure(CFG_TZDRAM_START, CFG_TZDRAM_SIZE, in imx_configure_tzasc()
/optee_os/core/arch/arm/plat-d02/
A Dconf.mk31 CFG_TZDRAM_START ?= 0x50400000
/optee_os/core/arch/arm/plat-hisilicon/
A Dconf.mk54 CFG_TZDRAM_START ?= 0x32600000
/optee_os/core/arch/arm/plat-rzn1/
A Dconf.mk19 CFG_TZDRAM_START ?= 0x88000000
/optee_os/core/arch/arm/plat-rpi3/
A Dconf.mk7 CFG_TZDRAM_START ?= 0x10100000
/optee_os/core/arch/arm/plat-rzg/
A Dconf.mk36 CFG_TZDRAM_START ?= 0x44100000

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