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Searched refs:CORE_MMU_PGDIR_SIZE (Results 1 – 25 of 33) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/
A Dmain.c53 CORE_MMU_PGDIR_SIZE);
66 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE));
70 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE));
74 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE));
78 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE));
82 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE),
83 CORE_MMU_PGDIR_SIZE);
90 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE),
91 CORE_MMU_PGDIR_SIZE);
96 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE),
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/optee_os/core/arch/arm/plat-uniphier/
A Dmain.c18 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
19 CORE_MMU_PGDIR_SIZE);
22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
23 CORE_MMU_PGDIR_SIZE);
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
27 CORE_MMU_PGDIR_SIZE);
45 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE); in main_init_gic()
47 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE); in main_init_gic()
/optee_os/core/arch/arm/plat-sprd/
A Dmain.c38 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
39 CORE_MMU_PGDIR_SIZE);
42 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
43 CORE_MMU_PGDIR_SIZE);
46 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
47 CORE_MMU_PGDIR_SIZE);
A Dplatform_config.h84 CORE_MMU_PGDIR_SIZE)
86 CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-zynqmp/
A Dmain.c54 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
55 CORE_MMU_PGDIR_SIZE);
58 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
59 CORE_MMU_PGDIR_SIZE);
62 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
63 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-poplar/
A Dplatform_config.h124 #define TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_PGDIR_SIZE)
125 #define TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_PGDIR_SIZE)
135 CORE_MMU_PGDIR_SIZE)
138 CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-imx/pm/
A Dpm-imx7.c113 map.region_size = CORE_MMU_PGDIR_SIZE; in pm_imx7_iram_tbl_init()
123 map.pa = ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE); in pm_imx7_iram_tbl_init()
125 CORE_MMU_PGDIR_SIZE); in pm_imx7_iram_tbl_init()
126 map.region_size = CORE_MMU_PGDIR_SIZE; in pm_imx7_iram_tbl_init()
127 map.size = CORE_MMU_PGDIR_SIZE; in pm_imx7_iram_tbl_init()
134 map.region_size = CORE_MMU_PGDIR_SIZE; in pm_imx7_iram_tbl_init()
135 map.size = CORE_MMU_PGDIR_SIZE; in pm_imx7_iram_tbl_init()
/optee_os/core/arch/arm/plat-synquacer/
A Dmain.c26 CORE_MMU_PGDIR_SIZE);
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
29 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-marvell/
A Dmain.c64 CORE_MMU_PGDIR_SIZE);
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c51 CORE_MMU_PGDIR_SIZE);
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-bcm/
A Dplatform_config.h55 #define BCM_DEVICE0_SIZE CORE_MMU_PGDIR_SIZE
57 #define BCM_DEVICE1_SIZE CORE_MMU_PGDIR_SIZE
/optee_os/core/arch/arm/plat-sam/
A Dmain.c49 CORE_MMU_PGDIR_SIZE);
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SFR_BASE, CORE_MMU_PGDIR_SIZE);
72 CORE_MMU_PGDIR_SIZE);
74 CORE_MMU_PGDIR_SIZE);
A Dsam_pl310.c38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-mediatek/
A Dmain.c26 CORE_MMU_PGDIR_SIZE);
28 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/include/mm/
A Dgeneric_ram_layout.h122 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE
157 #define TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_PGDIR_SIZE)
A Dcore_mmu.h36 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) macro
37 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1)
85 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE
248 register_phys_mem(type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
249 ROUNDUP(size + addr - ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
250 CORE_MMU_PGDIR_SIZE))
/optee_os/core/arch/arm/plat-ti/
A Dplatform_config.h141 CORE_MMU_PGDIR_SIZE)
145 CORE_MMU_PGDIR_SIZE)
/optee_os/core/arch/arm/plat-rzn1/
A Dmain.c35 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
36 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-ls/
A Dmain.c61 CORE_MMU_PGDIR_SIZE);
63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-amlogic/
A Dmain.c14 CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-imx/drivers/
A Dimx_caam.c15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CAAM_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
A Dhal_sec_perf.c136 register_phys_mem_pgdir(MEM_AREA_IO_SEC, MCU_BASE, CORE_MMU_PGDIR_SIZE);
137 register_phys_mem_pgdir(MEM_AREA_IO_SEC, MC_SCR_REGISTER, CORE_MMU_PGDIR_SIZE);
/optee_os/core/drivers/crypto/caam/hal/common/
A Dhal_cfg.c35 CORE_MMU_PGDIR_SIZE); in caam_hal_cfg_get_conf()
/optee_os/core/arch/arm/mm/
A Dpgt_cache.c443 vaddr_t e = MIN(p->vabase + CORE_MMU_PGDIR_SIZE, end); in clear_ctx_range_from_list()
476 const vaddr_t base = ROUNDDOWN(begin, CORE_MMU_PGDIR_SIZE); in pgt_alloc_unlocked()
483 p = pop_from_some_list(base + n * CORE_MMU_PGDIR_SIZE, ctx); in pgt_alloc_unlocked()
/optee_os/core/mm/
A Dvm.c74 granul = CORE_MMU_PGDIR_SIZE; in select_va_in_range()
97 granul = CORE_MMU_PGDIR_SIZE; in select_va_in_range()
128 b = ROUNDDOWN(b, CORE_MMU_PGDIR_SIZE); in get_num_req_pgts()
129 e = ROUNDUP(e, CORE_MMU_PGDIR_SIZE); in get_num_req_pgts()
170 vaddr_t begin = ROUNDDOWN(r->va, CORE_MMU_PGDIR_SIZE); in rem_um_region()
171 vaddr_t last = ROUNDUP(r->va + r->size, CORE_MMU_PGDIR_SIZE); in rem_um_region()
188 last = MIN(last, ROUNDDOWN(r2->va, CORE_MMU_PGDIR_SIZE)); in rem_um_region()
193 ROUNDUP(r2->va + r2->size, CORE_MMU_PGDIR_SIZE)); in rem_um_region()

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