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Searched refs:DRAM0_BASE (Results 1 – 19 of 19) sorted by relevance

/optee_os/core/arch/arm/plat-uniphier/
A Dmain.c29 #ifdef DRAM0_BASE
30 register_ddr(DRAM0_BASE, DRAM0_SIZE);
A Dplatform_config.h49 #define DRAM0_BASE (CFG_DRAM0_BASE + CFG_DRAM0_RSV_SIZE) macro
/optee_os/core/arch/arm/plat-vexpress/
A Dplatform_config.h88 #define DRAM0_BASE 0x80000000 macro
105 #define DRAM0_BASE 0x80000000 macro
A Dmain.c39 #ifdef DRAM0_BASE
40 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-zynqmp/
A Dmain.c74 register_ddr(DRAM0_BASE, 0x80000000);
77 register_ddr(DRAM0_BASE, CFG_DDR_SIZE);
A Dplatform_config.h43 #define DRAM0_BASE 0 macro
/optee_os/core/arch/arm/plat-stm/
A Dplatform_config.h202 #define DRAM0_BASE (CFG_DDR_START + CFG_STM_RSV_DRAM_STARTBYTES) macro
203 #define DRAM0_SIZE (STM_SECDDR_BASE - DRAM0_BASE)
A Dmain.c29 #ifdef DRAM0_BASE
30 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-rpi3/
A Dplatform_config.h68 #define DRAM0_BASE 0x00000000 macro
/optee_os/core/arch/arm/plat-d02/
A Dplatform_config.h67 #define DRAM0_BASE 0x00000000 macro
/optee_os/core/arch/arm/plat-synquacer/
A Dplatform_config.h26 #define DRAM0_BASE 0x80000000 macro
/optee_os/core/arch/arm/plat-totalcompute/
A Dplatform_config.h26 #define DRAM0_BASE 0x80000000 macro
A Dmain.c29 register_ddr(DRAM0_BASE, DRAM0_SIZE);
/optee_os/core/arch/arm/plat-sprd/
A Dplatform_config.h51 #define DRAM0_BASE 0x80000000 macro
/optee_os/core/arch/arm/plat-mediatek/
A Dplatform_config.h35 #define DRAM0_BASE 0x40000000 macro
/optee_os/core/arch/arm/plat-poplar/
A Dplatform_config.h99 #define DRAM0_BASE 0x00000000 macro
/optee_os/core/arch/arm/plat-hikey/
A Dplatform_config.h107 #define DRAM0_BASE 0x00000000 macro
A Dmain.c36 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC);
/optee_os/core/arch/arm/plat-ti/
A Dplatform_config.h9 #define DRAM0_BASE 0x80000000 macro

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