Home
last modified time | relevance | path

Searched refs:DRAM1_BASE (Results 1 – 12 of 12) sorted by relevance

/optee_os/core/arch/arm/plat-uniphier/
A Dmain.c32 #ifdef DRAM1_BASE
33 register_ddr(DRAM1_BASE, DRAM1_SIZE);
/optee_os/core/arch/arm/plat-vexpress/
A Dplatform_config.h91 #define DRAM1_BASE 0x880000000UL macro
108 #define DRAM1_BASE 0x880000000UL macro
A Dmain.c42 #ifdef DRAM1_BASE
43 register_ddr(DRAM1_BASE, DRAM1_SIZE);
/optee_os/core/arch/arm/plat-stm/
A Dplatform_config.h205 #define DRAM1_BASE STM_SECDDR_END macro
206 #define DRAM1_SIZE ((CFG_DDR_START - DRAM1_BASE) + CFG_DDR_SIZE)
A Dmain.c32 #ifdef DRAM1_BASE
33 register_ddr(DRAM1_BASE, DRAM1_SIZE);
/optee_os/core/arch/arm/plat-d02/
A Dplatform_config.h70 #define DRAM1_BASE 0x51800000 macro
/optee_os/core/arch/arm/plat-totalcompute/
A Dplatform_config.h29 #define DRAM1_BASE 0x8080000000ULL macro
A Dmain.c30 register_ddr(DRAM1_BASE, DRAM1_SIZE);
/optee_os/core/arch/arm/plat-zynqmp/
A Dplatform_config.h47 #define DRAM1_BASE 0x800000000 macro
A Dmain.c75 register_ddr(DRAM1_BASE, CFG_DDR_SIZE - 0x80000000);
/optee_os/core/arch/arm/plat-hikey/
A Dplatform_config.h110 #define DRAM1_BASE 0x40000000 macro
A Dmain.c38 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC);

Completed in 10 milliseconds