| /optee_os/core/arch/arm/plat-rockchip/ |
| A D | platform_config.h | 20 #define GIC_BASE 0x32010000 macro
22 #define GICD_BASE (GIC_BASE + 0x1000)
23 #define GICC_BASE (GIC_BASE + 0x2000)
48 #define GIC_BASE (MMIO_BASE + 0x06E00000) macro
50 #define GICD_BASE GIC_BASE
51 #define GICR_BASE (GIC_BASE + SIZE_M(1))
70 #define GIC_BASE 0xff130000 macro
72 #define GICD_BASE (GIC_BASE + 0x1000)
73 #define GICC_BASE (GIC_BASE + 0x2000)
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| /optee_os/core/arch/arm/plat-ls/ |
| A D | platform_config.h | 59 #define GIC_BASE 0x01400000 macro
68 #define GIC_BASE 0x01400000 macro
77 #define GIC_BASE 0x01400000 macro
86 #define GIC_BASE 0x06000000 macro
95 #define GIC_BASE 0x06000000 macro
104 #define GIC_BASE 0x06000000 macro
113 #define GIC_BASE 0x06000000 macro
122 #define GIC_BASE 0x06000000 macro
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| A D | main.c | 63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
183 gic_base = GIC_BASE; in main_init_gic()
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| /optee_os/core/arch/arm/plat-marvell/ |
| A D | platform_config.h | 60 #define GIC_BASE GIC_DIST_BASE macro
72 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
73 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
98 #define GIC_BASE GIC_DIST_BASE macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
104 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
119 #define GIC_BASE 0x801000000000ll macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
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| A D | main.c | 70 #ifdef GIC_BASE
82 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
87 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-vexpress/ |
| A D | platform_config.h | 17 #define GIC_BASE 0x2c000000 macro
31 #define GIC_BASE 0x2c010000 macro
57 #define GIC_BASE 0x08000000 macro
70 #define GIC_BASE 0x08000000 macro
134 #ifdef GIC_BASE
135 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
136 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| A D | main.c | 46 #ifdef GIC_BASE
56 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
58 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| A D | platform_config.h | 16 #define GIC_BASE 0x30000000 macro
39 #ifdef GIC_BASE
40 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
41 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| /optee_os/core/arch/arm/plat-sprd/ |
| A D | main.c | 42 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
46 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
56 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
58 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-mediatek/ |
| A D | platform_config.h | 22 #define GIC_BASE 0x10220000 macro
40 #define GIC_BASE 0x0C000000 macro
54 #define GIC_BASE 0x10310000 macro
68 #define GIC_BASE 0x0C000000 macro
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| A D | main.c | 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
35 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
37 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-uniphier/ |
| A D | main.c | 22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
44 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
46 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-rzn1/ |
| A D | platform_config.h | 17 #define GIC_BASE 0x44100000 macro
20 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
21 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
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| /optee_os/core/arch/arm/plat-sunxi/ |
| A D | main.c | 47 #ifdef GIC_BASE
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
85 #ifdef GIC_BASE
134 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC, 1); in main_init_gic()
135 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC, 1); in main_init_gic()
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| /optee_os/core/arch/arm/plat-zynqmp/ |
| A D | main.c | 58 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
62 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
84 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
86 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| A D | platform_config.h | 54 #define GIC_BASE 0xF9010000 macro
72 #define GIC_BASE 0xF9010000 macro
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| /optee_os/core/arch/arm/plat-aspeed/ |
| A D | platform_ast2600.c | 51 GIC_BASE + GICD_OFFSET,
55 GIC_BASE + GICC_OFFSET,
77 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, in main_init_gic()
79 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-imx/ |
| A D | main.c | 55 #ifdef GIC_BASE
56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
135 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC, in main_init_gic()
137 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC, in main_init_gic()
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| /optee_os/core/arch/arm/plat-zynq7k/ |
| A D | platform_config.h | 38 #define GIC_BASE 0xF8F00000 macro
41 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
42 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
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| A D | main.c | 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
150 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
152 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-imx/registers/ |
| A D | imx6.h | 84 #define GIC_BASE 0x00A00000 macro
98 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
99 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
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| /optee_os/core/arch/arm/plat-synquacer/ |
| A D | main.c | 27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
47 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
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| /optee_os/core/arch/arm/plat-imx/pm/ |
| A D | pm-imx7.c | 132 map.pa = GIC_BASE; in pm_imx7_iram_tbl_init()
133 map.va = (vaddr_t)phys_to_virt((paddr_t)GIC_BASE, MEM_AREA_IO_SEC, 1); in pm_imx7_iram_tbl_init()
182 p->gic_va_base = core_mmu_get_va(GIC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
183 p->gic_pa_base = GIC_BASE; in imx7_suspend_init()
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| /optee_os/core/arch/arm/plat-stm32mp1/ |
| A D | main.c | 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE);
197 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; in get_gicc_base()
204 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; in get_gicd_base()
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| /optee_os/core/arch/arm/plat-amlogic/ |
| A D | platform_config.h | 14 #define GIC_BASE 0xFFC01000 macro
|