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Searched refs:MCFGR (Results 1 – 7 of 7) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_ctrl.c17 BACKUP_REG(MCFGR, 1, 0, 0),
29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
42 io_mask32(baseaddr + MCFGR, MCFGR_AXIPIPE(1), BM_MCFGR_AXIPIPE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_ctrl.c16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_ctrl.c15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
A Dctrl_regs.h13 #define MCFGR 0x0004 macro
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/registers/
A Dctrl_regs.h13 #define MCFGR 0x0004 macro
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
A Dctrl_regs.h13 #define MCFGR 0x0004 macro
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
A Dctrl_regs.h13 #define MCFGR 0x0004 macro

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