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Searched refs:MEM_AREA_IO_SEC (Results 1 – 25 of 84) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/
A Dmain.c56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE,
69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE,
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE,
77 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE,
86 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE);
95 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
123 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC, 0x10000); in main_init_gic()
135 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC, in main_init_gic()
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/optee_os/core/arch/arm/plat-sunxi/
A Dmain.c48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE);
70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE,
75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE);
80 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE);
106 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC, in tzpc_init()
134 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC, 1); in main_init_gic()
135 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC, 1); in main_init_gic()
167 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC, in smc_base()
/optee_os/core/arch/arm/plat-rzn1/
A Dmain.c35 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
36 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
50 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
51 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
70 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, in rzn1_tz_init()
72 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, in rzn1_tz_init()
96 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
98 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
/optee_os/core/arch/arm/plat-zynqmp/
A Dmain.c53 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
61 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE);
85 MEM_AREA_IO_SEC, 1); in main_init_gic()
87 MEM_AREA_IO_SEC, 1); in main_init_gic()
107 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in plat_rpmb_key_is_ready()
/optee_os/core/arch/arm/plat-imx/pm/
A Dpm-imx7.c111 map.va = (vaddr_t)phys_to_virt(phys_addr[i], MEM_AREA_IO_SEC, in pm_imx7_iram_tbl_init()
115 map.type = MEM_AREA_IO_SEC; in pm_imx7_iram_tbl_init()
162 p->ccm_va_base = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
164 p->ddrc_va_base = core_mmu_get_va(DDRC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
166 p->ddrc_phy_va_base = core_mmu_get_va(DDRC_PHY_BASE, MEM_AREA_IO_SEC, in imx7_suspend_init()
169 p->src_va_base = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
172 MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
174 p->gpc_va_base = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
178 p->snvs_va_base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
180 p->lpsr_va_base = core_mmu_get_va(LPSR_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
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A Dcpuidle-imx7d.c53 p->ddrc_va_base = core_mmu_get_va(DDRC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
55 p->ccm_va_base = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
57 p->anatop_va_base = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
59 p->src_va_base = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
62 MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
64 p->gpc_va_base = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
66 p->gic_va_base = core_mmu_get_va(GIC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
142 MEM_AREA_IO_SEC, sizeof(uint32_t)); in get_online_cpus()
/optee_os/core/arch/arm/plat-marvell/
A Dmain.c63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
66 register_phys_mem(MEM_AREA_IO_SEC, PLAT_MARVELL_FUSF_FUSE_BASE,
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
83 MEM_AREA_IO_SEC, 1); in main_init_gic()
88 MEM_AREA_IO_SEC, 1); in main_init_gic()
123 MEM_AREA_IO_SEC, sizeof(hwkey->data)); in tee_otp_get_hw_unique_key()
/optee_os/core/arch/arm/plat-bcm/
A Dmain.c22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE);
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE4_BASE, BCM_DEVICE4_SIZE);
86 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-vexpress/
A Dmain.c32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
57 MEM_AREA_IO_SEC, GIC_CPU_REG_SIZE); in main_init_gic()
59 MEM_AREA_IO_SEC, GIC_DIST_REG_SIZE); in main_init_gic()
179 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
187 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); in init_tzc400()
211 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, in release_secondary_early_hpen()
/optee_os/core/arch/arm/plat-uniphier/
A Dmain.c17 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
45 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE); in main_init_gic()
47 MEM_AREA_IO_SEC, CORE_MMU_PGDIR_SIZE); in main_init_gic()
/optee_os/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c50 register_phys_mem(MEM_AREA_IO_SEC,
54 register_phys_mem(MEM_AREA_IO_SEC,
58 register_phys_mem(MEM_AREA_IO_SEC,
78 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE); in main_init_gic()
80 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE); in main_init_gic()
110 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE); in plat_primary_init_early()
/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
105 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
151 MEM_AREA_IO_SEC, 1); in main_init_gic()
153 MEM_AREA_IO_SEC, 1); in main_init_gic()
186 MEM_AREA_IO_SEC, in write_slcr()
207 MEM_AREA_IO_SEC, in read_slcr()
/optee_os/core/drivers/
A Dhi16xx_rng.c35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ALG_SC_BASE, ALG_SC_REG_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_REG_SIZE);
42 vaddr_t alg = (vaddr_t)phys_to_virt(ALG_SC_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
44 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
79 r = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, 1) + in hw_get_random_byte()
A Dzynqmp_csudma.c43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSUDMA_BASE, CSUDMA_SIZE);
47 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in csudma_clear_intr()
61 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_sync()
85 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_prepare()
100 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_unprepare()
111 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_transfer()
A Dzynqmp_csu_puf.c31 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_regenerate()
33 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_regenerate()
55 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_reset()
63 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_init()
/optee_os/core/arch/arm/plat-sprd/
A Dmain.c41 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
45 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
57 MEM_AREA_IO_SEC, 1); in main_init_gic()
59 MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-k3/
A Dmain.c23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
33 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, in main_init_gic()
35 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, in main_init_gic()
/optee_os/core/arch/arm/plat-rcar/
A Dmain.c39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PRR_BASE, SMALL_PAGE_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
/optee_os/core/arch/arm/plat-mediatek/
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
36 MEM_AREA_IO_SEC, 1); in main_init_gic()
38 MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-ti/
A Dmain.c33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
44 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, in main_init_gic()
46 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, in main_init_gic()
98 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC, 1); in init_sec_mon()
/optee_os/core/arch/arm/plat-sam/
A Dmain.c48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SFR_BASE, CORE_MMU_PGDIR_SIZE);
65 va = phys_to_virt(SFR_BASE, MEM_AREA_IO_SEC, 1); in sam_sfr_base()
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX32,
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX64,
82 va = phys_to_virt(AT91C_BASE_MATRIX32, MEM_AREA_IO_SEC, in matrix32_base()
95 va = phys_to_virt(AT91C_BASE_MATRIX64, MEM_AREA_IO_SEC, in matrix64_base()
/optee_os/core/arch/arm/plat-stm/
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE);
26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE);
93 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
141 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
142 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-hisilicon/
A Dmain.c18 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
21 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
24 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
/optee_os/core/arch/arm/plat-rzg/
A Dmain.c14 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
16 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
/optee_os/core/arch/arm/plat-rockchip/
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE);
33 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
38 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()

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