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Searched refs:NSEC_DDR_0_SIZE (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/arch/arm/plat-rzg/
A Dplatform_config.h23 #define NSEC_DDR_0_SIZE 0x78200000 macro
28 #define NSEC_DDR_0_SIZE 0x78200000 macro
35 #define NSEC_DDR_0_SIZE 0x78200000 macro
42 #define NSEC_DDR_0_SIZE 0x78200000 macro
A Dmain.c18 register_dynamic_shm(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
/optee_os/core/arch/arm/plat-rcar/
A Dplatform_config.h49 #define NSEC_DDR_0_SIZE 0x38200000 macro
59 #define NSEC_DDR_0_SIZE 0x78200000 macro
69 #define NSEC_DDR_0_SIZE 0x78200000 macro
75 #define NSEC_DDR_0_SIZE 0x78200000 macro
A Dmain.c49 register_ddr(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);

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