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Searched refs:RCC_MP_AHB5ENSETR (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/arch/arm/plat-stm32mp1/
A Drng_seed.c33 io_setbits32(rcc + RCC_MP_AHB5ENSETR, RCC_MP_AHB5ENSETR_RNG1EN); in plat_rng_init()
/optee_os/core/drivers/clk/
A Dclk-stm32mp15.c367 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5),
368 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5),
369 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5),
370 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL),
371 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _HCLK5),
/optee_os/core/include/drivers/
A Dstm32mp1_rcc.h66 #define RCC_MP_AHB5ENSETR 0x210 macro

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