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Searched refs:SHIFT_U32 (Results 1 – 25 of 54) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/registers/
A Dimx6-crm.h507 SHIFT_U32(0x3, BS_CCM_CLPCR_LPM)
573 SHIFT_U32(0x7, BS_CCM_CCOSR_CKO2_DIV)
585 SHIFT_U32(0x7, BS_CCM_CCOSR_CKOL_DIV)
607 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ1)
610 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ2)
613 SHIFT_U32(3, BS_CCM_CCGR0_APBHDMA)
616 SHIFT_U32(3, BS_CCM_CCGR0_ASRC)
759 SHIFT_U32(3, BS_CCM_CCGR4_PWM1)
762 SHIFT_U32(3, BS_CCM_CCGR4_PWM2)
765 SHIFT_U32(3, BS_CCM_CCGR4_PWM3)
[all …]
A Dimx8m-crm.h19 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
21 SHIFT_U32(0, BS_CCM_CCGRx_SETTING(idx))
25 SHIFT_U32(0x2, BS_CCM_CCGRx_SETTING(idx))
27 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
A Dimx6-dcp.h89 #define DCP_CONTROL1_HASH_SELECT_SHA256 SHIFT_U32(2, 16)
91 #define DCP_CONTROL1_HASH_SELECT_SHA1 SHIFT_U32(0, 16)
93 #define DCP_CONTROL1_CIPHER_MODE_ECB SHIFT_U32(0, 4)
95 #define DCP_CONTROL1_KEY_SELECT_OTP_CRYPTO SHIFT_U32(0xfe, 8)
A Dimx7-crm.h41 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
43 SHIFT_U32(0, BS_CCM_CCGRx_SETTING(idx))
47 SHIFT_U32(0x2, BS_CCM_CCGRx_SETTING(idx))
49 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
/optee_os/core/include/drivers/sam/
A Dat91_ddr.h15 #define AT91_DDRSDRC_MODE SHIFT_U32(0x7, 0)
32 #define AT91_DDRSDRC_NC SHIFT_U32(3, 0)
33 #define AT91_DDRSDRC_NC_SDR8 SHIFT_U32(0, 0)
42 #define AT91_DDRSDRC_NR SHIFT_U32(3, 2)
43 #define AT91_DDRSDRC_NR_11 SHIFT_U32(0, 2)
45 #define AT91_DDRSDRC_NR_13 SHIFT_U32(2, 2)
46 #define AT91_DDRSDRC_NR_14 SHIFT_U32(3, 2)
48 #define AT91_DDRSDRC_CAS SHIFT_U32(7, 4)
49 #define AT91_DDRSDRC_CAS_2 SHIFT_U32(2, 4)
50 #define AT91_DDRSDRC_CAS_3 SHIFT_U32(3, 4)
[all …]
/optee_os/core/drivers/crypto/caam/hal/common/registers/
A Drng_regs.h20 #define BM_TRNG_MCTL_SAMP_MODE SHIFT_U32(0x3, 0)
22 #define TRNG_MCTL_SAMP_MODE_RAW_ES_SC SHIFT_U32(1, 0)
26 #define BM_TRNG_SDCTL_ENT_DLY SHIFT_U32(0xFFFF, 16)
41 #define BM_TRNG_RTSCMISC_RTY_CNT SHIFT_U32(0xF, 16)
43 #define BM_TRNG_RTSCMISC_LRUN_MAX SHIFT_U32(0xFF, 0)
48 #define BM_TRNG_RTPKRRNG_PKR_RNG SHIFT_U32(0xFFFF, 0)
58 #define BM_TRNG_RTSCML_MONO_RNG SHIFT_U32(0xFFFF, 16)
60 #define BM_TRNG_RTSCML_MONO_MAX SHIFT_U32(0xFFFF, 0)
67 #define BM_TRNG_RTSCR1L_RUN1_MAX SHIFT_U32(0x7FFF, 0)
88 #define BM_TRNG_RTSCR4L_RUN4_MAX SHIFT_U32(0xFFF, 0)
[all …]
A Dversion_regs.h14 #define BM_CTPR_MS_RNG_I SHIFT_U32(0x7, 8)
23 #define BM_SMVID_MS_MAX_NPAG SHIFT_U32(0x3FF, 16)
25 #define BM_SMVID_MS_NPRT SHIFT_U32(0xF, 12)
29 #define BM_SMVID_LS_PSIZ SHIFT_U32(0x7, 16)
34 #define BM_CCBVID_CAAM_ERA SHIFT_U32(0xFF, 24)
39 #define BM_CHAVID_LS_RNGVID SHIFT_U32(0xF, 16)
41 #define BM_CHAVID_LS_MDVID SHIFT_U32(0xF, 12)
43 #define CHAVID_LS_MDVID_LP256 SHIFT_U32(0, 12)
65 #define BM_MDHA_VERSION_MDVID SHIFT_U32(0xFF, 24)
67 #define MDHA_VERSION_MDVID_LP256 SHIFT_U32(0, 24)
[all …]
A Djr_regs.h42 #define BM_JRX_JRINTR_HALT SHIFT_U32(0x3, 2)
43 #define JRINTR_HALT_RESUME SHIFT_U32(0x2, 2)
44 #define JRINTR_HALT_ONGOING SHIFT_U32(0x1, 2)
45 #define JRINTR_HALT_DONE SHIFT_U32(0x2, 2)
50 #define JRX_JRCFGR_LS_ICTT(val) SHIFT_U32((val) & 0xFFFF, 16)
51 #define JRX_JRCFGR_LS_ICDCT(val) SHIFT_U32((val) & 0xFF, 8)
/optee_os/core/drivers/crypto/caam/include/
A Dcaam_desc_defines.h15 #define CMD_TYPE(cmd) SHIFT_U32((cmd) & 0x1F, 27)
17 #define CMD_CLASS(val) SHIFT_U32((val) & 0x3, 25)
403 #define ALGO_DECRYPT SHIFT_U32(0x0, 0)
404 #define ALGO_ENCRYPT SHIFT_U32(0x1, 0)
554 #define PKHA_ALG SHIFT_U32(0x8, 20)
624 #define PDB_RSA_ENC_SGT_F SHIFT_U32(1, 31)
625 #define PDB_RSA_ENC_SGT_G SHIFT_U32(1, 30)
631 #define PDB_RSA_DEC_SGT_G SHIFT_U32(1, 31)
649 #define PDB_PKGEN_PD1 SHIFT_U32(1, 25)
651 #define PDB_PKSIGN_PD1 SHIFT_U32(1, 22)
[all …]
A Dcaam_jr_status.h13 #define BM_JRSTA_SRC SHIFT_U32(0xF, 28)
16 #define JRSTA_SRC(src) SHIFT_U32(JRSTA_SRC_##src, 28)
25 #define JRSTA_CCB_GET_ERR(status) ((status) & SHIFT_U32(0xFF, 0))
26 #define JRSTA_CCB_CHAID_RNG SHIFT_U32(0x5, 4)
27 #define JRSTA_CCB_ERRID_HW SHIFT_U32(0xB, 0)
28 #define JRSTA_DECO_ERRID_FORMAT SHIFT_U32(0x88, 0)
29 #define JRSTA_DECO_INV_SIGNATURE SHIFT_U32(0x86, 0)
A Dcaam_desc_ccb_defines.h20 #define NFIFO_CLASS(cla) SHIFT_U32(NFIFO_CLASS_##cla & 0x3, 30)
29 #define NFIFO_STYPE(src) SHIFT_U32(NFIFO_STYPE_##src & 0x3, 24)
33 #define NFIFO_DTYPE(data) SHIFT_U32(NFIFO_DTYPE_##data & 0xF, 20)
38 #define NFIFO_PTYPE(pad) SHIFT_U32(NFIFO_PTYPE_##pad & 0x7, 16)
42 #define NFIFO_DATA_LENGTH(len) SHIFT_U32((len) & 0xFFF, 0)
43 #define NFIFO_PAD_LENGTH(len) SHIFT_U32((len) & 0x7F, 0)
/optee_os/core/drivers/
A Dpl022_spi.c55 #define SSPCR0_SPH SHIFT_U32(1, 7)
56 #define SSPCR0_SPH1 SHIFT_U32(1, 7)
58 #define SSPCR0_SPO SHIFT_U32(1, 6)
61 #define SSPCR0_FRF SHIFT_U32(3, 4)
67 #define SSPCR1_SOD SHIFT_U32(1, 3)
70 #define SSPCR1_MS SHIFT_U32(1, 2)
82 #define SSPSR_BSY SHIFT_U32(1, 4)
83 #define SSPSR_RNF SHIFT_U32(1, 3)
84 #define SSPSR_RNE SHIFT_U32(1, 2)
85 #define SSPSR_TNF SHIFT_U32(1, 1)
[all …]
A Dpl061_gpio.c34 #define GPIOIE_ENABLED SHIFT_U32(1, 0)
35 #define GPIOIE_MASKED SHIFT_U32(0, 0)
36 #define GPIOAFSEL_HW SHIFT_U32(1, 0)
37 #define GPIOAFSEL_SW SHIFT_U32(0, 0)
38 #define GPIODIR_OUT SHIFT_U32(1, 0)
39 #define GPIODIR_IN SHIFT_U32(0, 0)
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4)
16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4)
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0)
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16)
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0)
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0)
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16)
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0)
49 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4)
16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4)
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0)
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16)
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0)
/optee_os/core/tee/
A Duuid.c25 d->timeLow = SHIFT_U32(s[0], 24) | SHIFT_U32(s[1], 16) | in tee_uuid_from_octets()
26 SHIFT_U32(s[2], 8) | s[3]; in tee_uuid_from_octets()
27 d->timeMid = SHIFT_U32(s[4], 8) | s[5]; in tee_uuid_from_octets()
28 d->timeHiAndVersion = SHIFT_U32(s[6], 8) | s[7]; in tee_uuid_from_octets()
/optee_os/core/arch/arm/plat-stm/
A Dplatform_config.h100 #define SCU_CPUS_MASK (SHIFT_U32(1, CFG_TEE_CORE_NB_CORE) - 1)
103 #define SCU_NSAC_INIT (SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_SCU_SHIFT) | \
104 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_PTIMER_SHIFT) | \
105 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_GTIMER_SHIFT))
/optee_os/core/drivers/crypto/caam/hal/imx_8q/registers/
A Dctrl_regs.h19 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32((val) & (0x3FF), 19)
24 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32((val) & (0xF), 0)
29 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
A Dctrl_regs.h24 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32(((val) & 0x3FF), 19)
29 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32(((val) & 0xF), 0)
34 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/registers/
A Dctrl_regs.h24 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32(((val) & (0x3FF)), 19)
29 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32(((val) & (0xF)), 0)
34 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/arch/arm/plat-rockchip/
A Dcru.h31 #define CORE_SOFT_RESET(core) SHIFT_U32(0x100010, (core))
32 #define CORE_SOFT_RELEASE(core) SHIFT_U32(0x100000, (core))
33 #define CORE_HELD_IN_RESET(core) SHIFT_U32(0x000010, (core))
A Dgrf.h12 #define CORE_WFE_MASK(core) SHIFT_U32(0x02, (core))
13 #define CORE_WFI_MASK(core) SHIFT_U32(0x20, (core))
A Dcommon.h23 #define BITS_WMSK(msk, shift) SHIFT_U32(msk, (shift) + REG_MSK_SHIFT)
25 (SHIFT_U32(bits, shift) | BITS_WMSK(msk, shift))
/optee_os/core/drivers/clk/sam/
A Dat91_pmc.h232 SHIFT_U32(n, AT91_PMC_AUDIO_PLL_ND_OFFSET)
237 SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
245 SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
251 SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
258 SHIFT_U32(n, AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
/optee_os/core/include/drivers/
A Dtzc400.h168 #define REG_ATTR_FILTER_BIT(x) SHIFT_U32(BIT(x), REG_ATTR_F_EN_SHIFT)
169 #define REG_ATTR_FILTER_BIT_ALL SHIFT_U32(REG_ATTR_F_EN_MASK, \
179 SHIFT_U32(BIT(id & REGION_ID_ACCESS_NSAID_ID_MASK), \
182 SHIFT_U32(BIT(id & REGION_ID_ACCESS_NSAID_ID_MASK), \

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