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Searched refs:SLCR_BASE (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
185 va = (vaddr_t)phys_to_virt(SLCR_BASE, in write_slcr()
206 va = (vaddr_t)phys_to_virt(SLCR_BASE, in read_slcr()
A Dplatform_config.h44 #define SLCR_BASE 0xF8000000 macro

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