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Searched refs:U (Results 1 – 25 of 57) sorted by relevance

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/optee_os/core/include/drivers/
A Dtzc380.h52 #define FAIL_ID U(0x02c)
57 #define REGION_SETUP_LOW_OFF(n) (U(0x100) + (n) * U(0x10))
58 #define REGION_SETUP_HIGH_OFF(n) (U(0x104) + (n) * U(0x10))
59 #define REGION_ATTRIBUTES_OFF(n) (U(0x108) + (n) * U(0x10))
62 #define PID0_OFF U(0xfe0)
63 #define PID1_OFF U(0xfe4)
64 #define PID2_OFF U(0xfe8)
65 #define PID3_OFF U(0xfec)
66 #define PID4_OFF U(0xfd0)
67 #define CID0_OFF U(0xff0)
[all …]
A Dtzc400.h96 #define PID0_OFF U(0xfe0)
97 #define PID1_OFF U(0xfe4)
98 #define PID2_OFF U(0xfe8)
99 #define PID3_OFF U(0xfec)
100 #define PID4_OFF U(0xfd0)
101 #define PID5_OFF U(0xfd4)
102 #define PID6_OFF U(0xfd8)
103 #define PID7_OFF U(0xfdc)
104 #define CID0_OFF U(0xff0)
105 #define CID1_OFF U(0xff4)
[all …]
A Dls_i2c.h23 #define I2C_IBCR_MDIS U(0x80)
26 #define I2C_IBCR_IBIE U(0x40)
37 #define I2C_IBCR_MSSL U(0x20)
40 #define I2C_IBCR_TXRX U(0x10)
60 #define I2C_IBCR_RSTA U(0x04)
66 #define I2C_IBSR_TCF U(0x80)
69 #define I2C_IBSR_IBB U(0x20)
72 #define I2C_IBSR_IBAL U(0x10)
75 #define I2C_IBSR_IBIF U(0x02)
82 #define I2C_IBSR_RXAK U(0x01)
[all …]
A Dls_gpio.h18 #define MAX_GPIO_PINS U(31)
24 #define GPIODIR U(0x0) /* direction register */
25 #define GPIOODR U(0x4) /* open drain register */
26 #define GPIODAT U(0x8) /* data register */
27 #define GPIOIER U(0xc) /* interrupt event register */
28 #define GPIOIMR U(0x10) /* interrupt mask register */
29 #define GPIOICR U(0x14) /* interrupt control register */
30 #define GPIOIBE U(0x18) /* input buffer enable register */
A Dstm32_i2c.h25 #define I2C_STANDARD_RATE U(100000)
26 #define I2C_FAST_RATE U(400000)
27 #define I2C_FAST_PLUS_RATE U(1000000)
85 #define I2C_ERROR_NONE U(0x0)
132 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */
133 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */
134 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */
135 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */
136 #define STM32_I2C_DIGITAL_FILTER_MAX U(16)
/optee_os/core/arch/arm/include/kernel/
A Dtz_ssvce_def.h58 #define PL310_8_WAYS U(8)
62 #define PL310_CTRL U(0x100)
97 #define SCU_CTRL U(0x00)
98 #define SCU_CONFIG U(0x04)
99 #define SCU_POWER U(0x08)
100 #define SCU_INV_SEC U(0x0C)
101 #define SCU_FILT_SA U(0x40)
102 #define SCU_FILT_EA U(0x44)
103 #define SCU_SAC U(0x50)
104 #define SCU_NSAC U(0x54)
[all …]
A Dtz_proc_def.h16 #define CPU_ID0 U(0x00000000)
17 #define CPU_ID1 U(0x00000001)
22 #define CP15_CONFIG_NS_MASK U(0x00000001)
23 #define CP15_CONFIG_IRQ_MASK U(0x00000002)
24 #define CP15_CONFIG_FIQ_MASK U(0x00000004)
25 #define CP15_CONFIG_EA_MASK U(0x00000008)
26 #define CP15_CONFIG_FW_MASK U(0x00000010)
61 #define CP15_CACHE_ADDR_R_BIT U(12)
87 #define LINE_FIELD_OFFSET U(5)
89 #define LINE_FIELD_OVERFLOW U(13)
[all …]
A Dstmm_sp.h24 #define STMM_MEM_ATTR_ACCESS_MASK U(0x3)
25 #define STMM_MEM_ATTR_ACCESS_NONE U(0)
26 #define STMM_MEM_ATTR_ACCESS_RW U(1)
27 #define STMM_MEM_ATTR_ACCESS_RO U(3)
29 #define STMM_MEM_ATTR_EXEC U(0)
/optee_os/core/arch/arm/include/
A Darm64.h21 #define TTBR_ASID_MASK U(0xff)
22 #define TTBR_ASID_SHIFT U(48)
24 #define CLIDR_LOUIS_SHIFT U(21)
25 #define CLIDR_LOC_SHIFT U(24)
26 #define CLIDR_FIELD_WIDTH U(3)
28 #define CSSELR_LEVEL_SHIFT U(1)
37 #define DAIF_F_SHIFT U(6)
121 #define TCR_SHX_NSH U(0x0)
123 #define TCR_SHX_OSH U(0x2)
125 #define TCR_SHX_ISH U(0x3)
[all …]
A Darm.h36 #define MPIDR_AFF0_SHIFT U(0)
38 #define MPIDR_AFF1_SHIFT U(8)
40 #define MPIDR_AFF2_SHIFT U(16)
43 #define MPIDR_MT_SHIFT U(24)
62 #define CTR_CWG_SHIFT U(24)
63 #define CTR_CWG_MASK U(0xf)
64 #define CTR_ERG_SHIFT U(20)
65 #define CTR_ERG_MASK U(0xf)
69 #define CTR_L1IP_SHIFT U(14)
70 #define CTR_L1IP_MASK U(0x3)
[all …]
A Dffa.h27 #define FFA_VERSION_MAJOR U(1)
28 #define FFA_VERSION_MAJOR_SHIFT U(16)
30 #define FFA_VERSION_MINOR U(0)
31 #define FFA_VERSION_MINOR_SHIFT U(0)
38 #define FFA_ERROR U(0x84000060)
42 #define FFA_VERSION U(0x84000063)
43 #define FFA_FEATURES U(0x84000064)
49 #define FFA_ID_GET U(0x84000069)
50 #define FFA_MSG_WAIT U(0x8400006B)
52 #define FFA_MSG_RUN U(0x8400006D)
[all …]
A Darm32.h101 #define PAR_PA_SHIFT U(12)
117 #define TTBCR_T0SZ_SHIFT U(0)
119 #define TTBCR_IRGN0_SHIFT U(8)
121 #define TTBCR_SH0_SHIFT U(12)
122 #define TTBCR_T1SZ_SHIFT U(16)
127 #define TTBCR_SH1_SHIFT U(28)
130 #define TTBCR_XRGNX_NC U(0x0)
139 #define TTBCR_SHX_NSH U(0x0)
141 #define TTBCR_SHX_OSH U(0x2)
143 #define TTBCR_SHX_ISH U(0x3)
[all …]
A Doptee_ffa.h34 #define OPTEE_FFA_YIELDING_CALL_BIT U(31)
150 #define OPTEE_FFA_YIELDING_CALL_RETURN_DONE U(0)
151 #define OPTEE_FFA_YIELDING_CALL_RETURN_RPC_CMD U(1)
152 #define OPTEE_FFA_YIELDING_CALL_RETURN_INTERRUPT U(2)
/optee_os/core/include/
A Doptee_rpc_cmd.h28 #define OPTEE_RPC_CMD_LOAD_TA U(0)
36 #define OPTEE_RPC_CMD_RPMB U(1)
41 #define OPTEE_RPC_CMD_FS U(2)
52 #define OPTEE_RPC_CMD_GET_TIME U(3)
82 #define OPTEE_RPC_CMD_SUSPEND U(5)
126 #define OPTEE_RPC_CMD_GPROF U(9)
192 #define OPTEE_RPC_FS_OPEN U(0)
201 #define OPTEE_RPC_FS_CREATE U(1)
209 #define OPTEE_RPC_FS_CLOSE U(2)
219 #define OPTEE_RPC_FS_READ U(3)
[all …]
A Doptee_msg.h21 #define OPTEE_MSG_ATTR_TYPE_NONE U(0x0)
80 #define OPTEE_MSG_ATTR_CACHE_SHIFT U(16)
251 #define OPTEE_MSG_UID_0 U(0x384fb3e0)
252 #define OPTEE_MSG_UID_1 U(0xe7f811e3)
253 #define OPTEE_MSG_UID_2 U(0xaf630002)
254 #define OPTEE_MSG_UID_3 U(0xa5d5c51b)
262 #define OPTEE_MSG_REVISION_MAJOR U(2)
263 #define OPTEE_MSG_REVISION_MINOR U(0)
335 #define OPTEE_MSG_CMD_OPEN_SESSION U(0)
338 #define OPTEE_MSG_CMD_CANCEL U(3)
[all …]
A Dbench.h18 #define TEE_BENCH_DIVIDER U(64)
21 #define TEE_BENCH_MAX_STAMPS U(32)
24 #define OPTEE_MSG_RPC_CMD_BENCH_REG_NEW U(0)
25 #define OPTEE_MSG_RPC_CMD_BENCH_REG_DEL U(1)
28 #define TEE_BENCH_CLIENT U(0x10000000)
29 #define TEE_BENCH_KMOD U(0x20000000)
30 #define TEE_BENCH_CORE U(0x30000000)
31 #define TEE_BENCH_UTEE U(0x40000000)
32 #define TEE_BENCH_DUMB_TA U(0xF0000001)
/optee_os/core/arch/arm/include/sm/
A Doptee_smc.h20 #define OPTEE_SMC_32 U(0)
21 #define OPTEE_SMC_64 U(0x40000000)
23 #define OPTEE_SMC_STD_CALL U(0)
25 #define OPTEE_SMC_OWNER_MASK U(0x3F)
26 #define OPTEE_SMC_OWNER_SHIFT U(24)
28 #define OPTEE_SMC_FUNC_MASK U(0xFFFF)
49 #define OPTEE_SMC_OWNER_ARCH U(0)
50 #define OPTEE_SMC_OWNER_CPU U(1)
51 #define OPTEE_SMC_OWNER_SIP U(2)
52 #define OPTEE_SMC_OWNER_OEM U(3)
[all …]
A Dpsci.h5 #define PSCI_VERSION_0_2 U(0x00000002)
6 #define PSCI_VERSION_1_0 U(0x00010000)
7 #define PSCI_VERSION_1_1 U(0x00010001)
8 #define PSCI_VERSION U(0x84000000)
9 #define PSCI_CPU_SUSPEND U(0x84000001)
10 #define PSCI_CPU_OFF U(0x84000002)
11 #define PSCI_CPU_ON U(0x84000003)
14 #define PSCI_MIGRATE U(0x84000005)
17 #define PSCI_SYSTEM_OFF U(0x84000008)
31 #define PSCI_NUM_CALLS U(21)
[all …]
/optee_os/lib/libmbedtls/mbedtls/library/
A Dpoly1305.c110 size_t offset = 0U; in poly1305_process()
311 ctx->acc[0] = 0U; in mbedtls_poly1305_starts()
312 ctx->acc[1] = 0U; in mbedtls_poly1305_starts()
313 ctx->acc[2] = 0U; in mbedtls_poly1305_starts()
314 ctx->acc[3] = 0U; in mbedtls_poly1305_starts()
315 ctx->acc[4] = 0U; in mbedtls_poly1305_starts()
319 ctx->queue_len = 0U; in mbedtls_poly1305_starts()
328 size_t offset = 0U; in mbedtls_poly1305_update()
335 if( ( remaining > 0U ) && ( ctx->queue_len > 0U ) ) in mbedtls_poly1305_update()
350 remaining = 0U; in mbedtls_poly1305_update()
[all …]
A Dchachapoly.c63 if( partial_block_len == 0U ) in chachapoly_pad_aad()
83 if( partial_block_len == 0U ) in chachapoly_pad_ciphertext()
98 ctx->aad_len = 0U; in mbedtls_chachapoly_init()
99 ctx->ciphertext_len = 0U; in mbedtls_chachapoly_init()
111 ctx->aad_len = 0U; in mbedtls_chachapoly_free()
112 ctx->ciphertext_len = 0U; in mbedtls_chachapoly_free()
139 ret = mbedtls_chacha20_starts( &ctx->chacha20_ctx, nonce, 0U ); in mbedtls_chachapoly_starts()
158 ctx->aad_len = 0U; in mbedtls_chachapoly_starts()
159 ctx->ciphertext_len = 0U; in mbedtls_chachapoly_starts()
497 for( i = 0U; i < 1U; i++ ) in mbedtls_chachapoly_self_test()
A Dchacha20.c150 for( i = 0U; i < 10U; i++ ) in chacha20_block()
170 for( i = 0U; i < 16; i++ ) in chacha20_block()
255 size_t offset = 0U; in mbedtls_chacha20_update()
263 while( size > 0U && ctx->keystream_bytes_used < CHACHA20_BLOCK_SIZE_BYTES ) in mbedtls_chacha20_update()
280 for( i = 0U; i < 64U; i += 8U ) in mbedtls_chacha20_update()
297 if( size > 0U ) in mbedtls_chacha20_update()
303 for( i = 0U; i < size; i++) in mbedtls_chacha20_update()
381 0U,
539 for( i = 0U; i < 2U; i++ ) in mbedtls_chacha20_self_test()
/optee_os/core/lib/libtomcrypt/
A Dsm2-kep.c222 ecc_point *U = NULL; in sm2_kep_derive() local
242 U = ltc_ecc_new_point(); in sm2_kep_derive()
243 if (!U) { in sm2_kep_derive()
303 x2bar, U, ma, peer_key->dp.prime); in sm2_kep_derive()
315 ltc_res = ltc_ecc_mulmod(htA, U, U, peer_key->dp.A, peer_key->dp.prime, in sm2_kep_derive()
320 ltc_res = ltc_ecc_is_point_at_infinity(U, peer_key->dp.prime, &inf); in sm2_kep_derive()
330 mp_to_unsigned_bin2(U->x, xUyUZAZB, SM2_INT_SIZE_BYTES); in sm2_kep_derive()
333 mp_to_unsigned_bin2(U->y, xUyUZAZB + SM2_INT_SIZE_BYTES, in sm2_kep_derive()
365 res = sm2_kep_compute_S(S1, sizeof(S1), flag, U, in sm2_kep_derive()
389 res = sm2_kep_compute_S(p->conf_out, TEE_SM3_HASH_SIZE, flag, U, in sm2_kep_derive()
[all …]
/optee_os/core/arch/arm/include/mm/
A Dcore_mmu.h21 #define SMALL_PAGE_SHIFT U(12)
30 #define CORE_MMU_PGDIR_SHIFT U(21)
31 #define CORE_MMU_PGDIR_LEVEL U(3)
33 #define CORE_MMU_PGDIR_SHIFT U(20)
34 #define CORE_MMU_PGDIR_LEVEL U(2)
54 #define CORE_MMU_BASE_TABLE_SHIFT U(30)
55 #define CORE_MMU_BASE_TABLE_LEVEL U(1)
57 #define CORE_MMU_BASE_TABLE_SHIFT U(39)
58 #define CORE_MMU_BASE_TABLE_LEVEL U(0)
73 U(8))
[all …]
/optee_os/lib/libmbedtls/core/
A Dsm2-kep.c295 mbedtls_ecp_point U = { }; in crypto_acipher_sm2_kep_derive() local
325 mbedtls_ecp_point_init(&U); in crypto_acipher_sm2_kep_derive()
399 mres = mbedtls_ecp_muladd(&grp, &U, &one, &PB, &x2bar, &RB); in crypto_acipher_sm2_kep_derive()
404 mres = mbedtls_ecp_mul(&grp, &U, &tA, &U, mbd_rand, NULL); in crypto_acipher_sm2_kep_derive()
412 mres = mbedtls_ecp_is_zero(&U); in crypto_acipher_sm2_kep_derive()
419 mres = mbedtls_mpi_write_binary(&U.X, xUyUZAZB, SM2_INT_SIZE_BYTES); in crypto_acipher_sm2_kep_derive()
424 mres = mbedtls_mpi_write_binary(&U.Y, xUyUZAZB + SM2_INT_SIZE_BYTES, in crypto_acipher_sm2_kep_derive()
458 res = sm2_kep_compute_S(S1, sizeof(S1), flag, &U, in crypto_acipher_sm2_kep_derive()
483 &U, xUyUZAZB + 2 * SM2_INT_SIZE_BYTES, in crypto_acipher_sm2_kep_derive()
496 mbedtls_ecp_point_free(&U); in crypto_acipher_sm2_kep_derive()
/optee_os/core/include/mm/
A Dtee_mmu_types.h33 #define TEE_MATTR_CACHE_MASK U(0x7)
34 #define TEE_MATTR_CACHE_SHIFT U(12)
36 #define TEE_MATTR_CACHE_NONCACHE U(0)
37 #define TEE_MATTR_CACHE_CACHED U(1)

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