Home
last modified time | relevance | path

Searched refs:_DIV_P (Results 1 – 1 of 1) sorted by relevance

/optee_os/core/drivers/clk/
A Dclk-stm32mp15.c181 _DIV_P, enumerator
488 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
750 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
755 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> in get_clock_rate()
780 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); in get_clock_rate()
820 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); in get_clock_rate()
892 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
901 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); in get_clock_rate()
910 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); in get_clock_rate()
919 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); in get_clock_rate()

Completed in 5 milliseconds