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/optee_os/core/drivers/clk/
A Dclk-stm32mp15.c255 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
263 .fixed = (_parent), \
279 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
287 .fixed = (_parent), \
304 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
312 .fixed = (_parent), \
315 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ argument
320 .parent = (_parent), \
321 .nb_parent = ARRAY_SIZE(_parent) \

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