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Searched refs:bank (Results 1 – 11 of 11) sorted by relevance

/optee_os/core/drivers/
A Dstm32_gpio.c56 vaddr_t base = stm32_get_gpio_bank_base(bank); in get_gpio_cfg()
57 struct clk *clk = stm32_get_gpio_bank_clk(bank); in get_gpio_cfg()
95 vaddr_t base = stm32_get_gpio_bank_base(bank); in set_gpio_cfg()
143 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, in stm32_pinctrl_load_active_cfg()
152 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, in stm32_pinctrl_load_standby_cfg()
161 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, in stm32_pinctrl_store_standby_cfg()
231 uint32_t bank = 0; in get_pinctrl_from_fdt() local
281 ckeck_gpio_bank(fdt, bank, pinctrl_node); in get_pinctrl_from_fdt()
286 ref->bank = (uint8_t)bank; in get_pinctrl_from_fdt()
397 assert(valid_gpio_config(bank, pin, true)); in stm32_gpio_get_input_level()
[all …]
A Dimx_ocotp.c78 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val) in imx_ocotp_read() argument
85 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) in imx_ocotp_read()
105 *val = io_read32(g_base_addr + OCOTP_SHADOW_OFFSET(bank, word)); in imx_ocotp_read()
107 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, *val); in imx_ocotp_read()
A Dstm32_bsec.c173 uint32_t bank = otp_bank_offset(otp_id); in check_no_error() local
175 if (io_read32(bsec_base() + BSEC_ERROR_OFF + bank) & bit) in check_no_error()
179 io_read32(bsec_base() + BSEC_DISTURBED_OFF + bank) & bit) in check_no_error()
446 uint32_t bank = otp_bank_offset(otp_id); in set_bsec_lock() local
448 vaddr_t lock_addr = bsec_base() + bank + lock_offset; in set_bsec_lock()
481 uint32_t bank = otp_bank_offset(otp_id); in read_bsec_lock() local
483 vaddr_t lock_addr = bsec_base() + bank + lock_offset; in read_bsec_lock()
A Dstm32_uart.c118 stm32mp_register_secure_gpio(pd->pinctrl[n].bank, in register_secure_uart()
128 stm32mp_register_non_secure_gpio(pd->pinctrl[n].bank, in register_non_secure_uart()
/optee_os/core/arch/arm/plat-stm32mp1/
A Dmain.c274 if (bank == GPIO_BANK_Z) in stm32_get_gpio_bank_base()
278 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_base()
282 (bank * GPIO_BANK_OFFSET); in stm32_get_gpio_bank_base()
287 if (bank == GPIO_BANK_Z) in stm32_get_gpio_bank_offset()
290 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_offset()
291 return bank * GPIO_BANK_OFFSET; in stm32_get_gpio_bank_offset()
296 if (bank == GPIO_BANK_Z) in stm32_get_gpio_bank_clock()
299 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_clock()
300 return GPIOA + bank; in stm32_get_gpio_bank_clock()
306 if (bank == GPIO_BANK_Z) in stm32_get_gpio_bank_clk()
[all …]
A Dstm32_util.h43 vaddr_t stm32_get_gpio_bank_base(unsigned int bank);
44 unsigned int stm32_get_gpio_bank_offset(unsigned int bank);
45 unsigned int stm32_get_gpio_bank_clock(unsigned int bank);
46 struct clk *stm32_get_gpio_bank_clk(unsigned int bank);
280 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
287 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
293 bool stm32mp_gpio_bank_is_secure(unsigned int bank);
296 bool stm32mp_gpio_bank_is_shared(unsigned int bank);
299 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank);
A Dshared_resources.c386 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_secure_gpio() argument
388 switch (bank) { in stm32mp_register_secure_gpio()
394 EMSG("GPIO bank %u cannot be secured", bank); in stm32mp_register_secure_gpio()
399 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_non_secure_gpio() argument
401 switch (bank) { in stm32mp_register_non_secure_gpio()
423 bool stm32mp_gpio_bank_is_shared(unsigned int bank) in stm32mp_gpio_bank_is_shared() argument
430 if (bank != GPIO_BANK_Z) in stm32mp_gpio_bank_is_shared()
440 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank) in stm32mp_gpio_bank_is_non_secure() argument
447 if (bank != GPIO_BANK_Z) in stm32mp_gpio_bank_is_non_secure()
457 bool stm32mp_gpio_bank_is_secure(unsigned int bank) in stm32mp_gpio_bank_is_secure() argument
[all …]
/optee_os/core/include/drivers/
A Dstm32_gpio.h70 uint8_t bank; member
121 void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int high);
132 stm32_gpio_set_output_level(pinctrl->bank, pinctrl->pin, high); in stm32_pinctrl_set_gpio_level()
142 int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin);
152 return stm32_gpio_get_input_level(pinctrl->bank, pinctrl->pin); in stm32_pinctrl_get_gpio_level()
163 void stm32_gpio_set_secure_cfg(unsigned int bank, unsigned int pin,
166 static inline void stm32_gpio_set_secure_cfg(unsigned int bank __unused, in stm32_gpio_set_secure_cfg()
182 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank);
A Dimx_ocotp.h21 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val);
/optee_os/core/arch/arm/dts/
A Dstm32mp151.dtsi1544 st,bank-name = "GPIOA";
1555 st,bank-name = "GPIOB";
1566 st,bank-name = "GPIOC";
1577 st,bank-name = "GPIOD";
1588 st,bank-name = "GPIOE";
1599 st,bank-name = "GPIOF";
1610 st,bank-name = "GPIOG";
1621 st,bank-name = "GPIOH";
1632 st,bank-name = "GPIOI";
1643 st,bank-name = "GPIOJ";
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/optee_os/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pmic.c595 stm32mp_register_non_secure_gpio(i2c_handle.pinctrl[n].bank, in register_non_secure_pmic()
606 stm32mp_register_secure_gpio(i2c_handle.pinctrl[n].bank, in register_secure_pmic()

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