Searched refs:ccm_base (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/drivers/crypto/caam/hal/imx_6_7/ |
| A D | hal_clk_mx6.c | 14 vaddr_t ccm_base = (vaddr_t)phys_to_virt(CCM_BASE, MEM_AREA_IO_SEC, in caam_hal_clk_enable() local
19 reg = io_read32(ccm_base + CCM_CCGR0); in caam_hal_clk_enable()
29 io_write32(ccm_base + CCM_CCGR0, reg); in caam_hal_clk_enable()
33 reg = io_read32(ccm_base + CCM_CCGR6); in caam_hal_clk_enable()
41 io_write32(ccm_base + CCM_CCGR6, reg); in caam_hal_clk_enable()
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| A D | hal_clk_mx7.c | 14 vaddr_t ccm_base = (vaddr_t)phys_to_virt(CCM_BASE, MEM_AREA_IO_SEC, 1); in caam_hal_clk_enable() local
17 io_write32(ccm_base + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_CAAM), in caam_hal_clk_enable()
20 io_write32(ccm_base + CCM_CCGRx_CLR(CCM_CLOCK_DOMAIN_CAAM), in caam_hal_clk_enable()
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| /optee_os/core/drivers/imx/dcp/ |
| A D | dcp.c | 64 vaddr_t ccm_base = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, in dcp_clk_enable() local
74 io_setbits32(ccm_base + CCM_CCGR0, DCP_CLK_ENABLE_MASK); in dcp_clk_enable()
83 io_clrbits32(ccm_base + CCM_CCGR0, DCP_CLK_ENABLE_MASK); in dcp_clk_enable()
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