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Searched refs:cfg (Results 1 – 25 of 33) sorted by relevance

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/optee_os/core/drivers/
A Dstpmic1.c737 cfg->mask = mask; in stpmic1_bo_voltage_cfg()
751 if ((value & cfg->mask) >= cfg->min_value) in stpmic1_bo_voltage_unpg()
754 return stpmic1_register_update(cfg->ctrl_reg, cfg->min_value, in stpmic1_bo_voltage_unpg()
755 cfg->mask); in stpmic1_bo_voltage_unpg()
776 assert(cfg->pd_reg); in stpmic1_bo_pull_down_unpg()
778 return stpmic1_register_update(cfg->pd_reg, cfg->pd_value, in stpmic1_bo_pull_down_unpg()
802 return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value, in stpmic1_bo_mask_reset_unpg()
866 assert(cfg->lp_reg); in stpmic1_lp_load_unpg()
945 cfg->mask = mask; in stpmic1_lp_voltage_cfg()
952 assert(cfg->lp_reg); in stpmic1_lp_voltage_unpg()
[all …]
A Dtzc400.c267 assert(tzc.base && cfg); in tzc_configure_region()
270 assert(((cfg->filters >> tzc.num_filters) == 0) && in tzc_configure_region()
278 assert(((cfg->top <= (UINT64_MAX >> (64 - tzc.addr_width))) && in tzc_configure_region()
279 (cfg->base < cfg->top))); in tzc_configure_region()
282 assert(((cfg->base | (cfg->top + 1)) & (4096 - 1)) == 0); in tzc_configure_region()
284 assert(cfg->sec_attr <= TZC_REGION_S_RDWR); in tzc_configure_region()
294 tzc_write_region_top_low(tzc.base, region, addr_low(cfg->top)); in tzc_configure_region()
299 (cfg->sec_attr << REG_ATTR_SEC_SHIFT) | in tzc_configure_region()
300 cfg->filters); in tzc_configure_region()
324 cfg->sec_attr = val32 >> REG_ATTR_SEC_SHIFT; in tzc_get_region_config()
[all …]
A Datmel_shdwc.c23 #define SHDW_WK_PIN(reg, cfg) ((reg) & \ argument
24 AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
25 #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1) argument
26 #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1) argument
27 #define SHDW_RTCWKEN(cfg) BIT((cfg)->mr_rtcwk_shift) argument
28 #define SHDW_RTTWKEN(cfg) BIT((cfg)->mr_rttwk_shift) argument
A Dstm32_gpio.c68 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
71 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; in get_gpio_cfg()
76 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
79 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; in get_gpio_cfg()
82 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & in get_gpio_cfg()
85 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> in get_gpio_cfg()
104 cfg->mode << (pin << 1)); in set_gpio_cfg()
112 cfg->ospeed << (pin << 1)); in set_gpio_cfg()
116 cfg->pupd << (pin << 1)); in set_gpio_cfg()
122 cfg->af << (pin << 2)); in set_gpio_cfg()
[all …]
A Dstm32_i2c.c321 cfg->cr1 = io_read32(base + I2C_CR1); in save_cfg()
322 cfg->cr2 = io_read32(base + I2C_CR2); in save_cfg()
323 cfg->oar1 = io_read32(base + I2C_OAR1); in save_cfg()
324 cfg->oar2 = io_read32(base + I2C_OAR2); in save_cfg()
338 io_write32(base + I2C_OAR1, cfg->oar1); in restore_cfg()
339 io_write32(base + I2C_CR2, cfg->cr2); in restore_cfg()
349 DMSG("CR1: %#"PRIx32, cfg->cr1); in dump_cfg()
350 DMSG("CR2: %#"PRIx32, cfg->cr2); in dump_cfg()
351 DMSG("OAR1: %#"PRIx32, cfg->oar1); in dump_cfg()
352 DMSG("OAR2: %#"PRIx32, cfg->oar2); in dump_cfg()
[all …]
A Dstm32_bsec.c661 struct stm32_bsec_static_cfg cfg = { }; in initialize_bsec() local
663 stm32mp_get_bsec_static_cfg(&cfg); in initialize_bsec()
665 bsec_dev.base.pa = cfg.base; in initialize_bsec()
666 bsec_dev.upper_base = cfg.upper_start; in initialize_bsec()
667 bsec_dev.max_id = cfg.max_id; in initialize_bsec()
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pmic.c89 struct stpmic1_bo_cfg cfg; member
188 struct stpmic1_lp_cfg cfg; member
206 struct regu_lp_config *cfg; member
245 state->cfg = realloc(state->cfg, in dt_get_regu_low_power_config()
247 if (!state->cfg) in dt_get_regu_low_power_config()
313 struct stpmic1_lp_cfg *cfg = &state->cfg[i].cfg; in stm32mp_pmic_apply_lp_config() local
316 stpmic1_lp_load_unpg(cfg)) in stm32mp_pmic_apply_lp_config()
320 stpmic1_lp_on_off_unpg(cfg, 1)) in stm32mp_pmic_apply_lp_config()
324 stpmic1_lp_on_off_unpg(cfg, 0)) in stm32mp_pmic_apply_lp_config()
328 stpmic1_lp_voltage_unpg(cfg)) in stm32mp_pmic_apply_lp_config()
[all …]
/optee_os/core/include/drivers/
A Dstpmic1.h235 int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg);
237 struct stpmic1_bo_cfg *cfg);
238 int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg);
241 struct stpmic1_bo_cfg *cfg);
242 int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg);
245 int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg);
248 int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg);
249 int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg);
251 int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg,
254 struct stpmic1_lp_cfg *cfg);
[all …]
A Dtzc400.h233 void tzc_configure_region(uint8_t region, const struct tzc_region_config *cfg);
234 TEE_Result tzc_get_region_config(uint8_t region, struct tzc_region_config *cfg);
/optee_os/mk/
A Dcheckconf.mk68 define cfg-vars-by-prefix
81 define cfg-make-define
92 define cfg-cmake-set
101 cfg-one-enabled = $(if $(filter y, $(foreach var,$(1),$($(var)))),y,n)
106 cfg-all-enabled = $(if $(strip $(1)),$(if $(call _cfg-all-enabled,$(1)),y,n),n)
121 cfg-depends-all = \
124 $(if $(filter y,$(call cfg-all-enabled,$(2))), \
136 cfg-depends-one = \
139 $(if $(filter y,$(call cfg-one-enabled,$(2))), \
152 cfg-enable-all-depends = \
[all …]
A Dconfig.mk311 $(eval $(call cfg-depends-all,CFG_REE_FS_TA_BUFFERED,CFG_REE_FS_TA))
507 $(call cfg-check-value,FTRACE_BUF_WHEN_FULL,shift stop wrap)
521 $(call cfg-depends-all,CFG_SYSCALL_FTRACE,CFG_FTRACE_SUPPORT)
560 CFG_SECSTOR_TA ?= $(call cfg-all-enabled,CFG_REE_FS CFG_WITH_USER_TA)
564 CFG_SECSTOR_TA_MGMT_PTA ?= $(call cfg-all-enabled,CFG_SECSTOR_TA)
565 $(eval $(call cfg-depends-all,CFG_SECSTOR_TA_MGMT_PTA,CFG_SECSTOR_TA))
571 $(eval $(call cfg-depends-all,CFG_SYSTEM_PTA,CFG_WITH_USER_TA))
729 CFG_DRIVERS_CLK_DT ?= $(call cfg-all-enabled,CFG_DRIVERS_CLK CFG_DT)
759 $(eval $(call cfg-depends-all,CFG_CORE_BTI,CFG_ARM64_core))
765 $(eval $(call cfg-depends-all,CFG_TA_BTI,CFG_ARM64_core))
[all …]
/optee_os/core/include/dt-bindings/dma/
A Dat91.h37 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) \ argument
38 (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
46 #define AT91_XDMAC_DT_GET_PER_IF(cfg) \ argument
47 (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
54 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ argument
/optee_os/core/
A Dcrypto.mk107 cryp-enable-all-depends = $(call cfg-enable-all-depends,$(strip $(1)),$(foreach v,$(2),CFG_CRYPTO_$…
113 cryp-dep-one = $(call cfg-depends-one,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
114 cryp-dep-all = $(call cfg-depends-all,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
188 _CFG_CORE_LTC_AES_DESC := $(call cfg-one-enabled, CFG_CRYPTO_XTS CFG_CRYPTO_CCM)
195 _CFG_CORE_LTC_SHA256_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA256_DESC \
198 _CFG_CORE_LTC_SHA384_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA384_DESC \
200 _CFG_CORE_LTC_SHA512_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA512_DESC \
203 _CFG_CORE_LTC_AES_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_AES_DESC \
219 ltc-one-enabled = $(call cfg-one-enabled,$(foreach v,$(1),_CFG_CORE_LTC_$(v)))
/optee_os/core/drivers/crypto/caam/
A Dsub.mk11 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_HASH_DRV CFG_NXP_CAAM_HMAC_DRV) += hash
12 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_CIPHER_DRV CFG_NXP_CAAM_CMAC_DRV) += cipher
/optee_os/core/arch/arm/plat-stm32mp1/
A Dmain.c209 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) in stm32mp_get_bsec_static_cfg() argument
211 cfg->base = BSEC_BASE; in stm32mp_get_bsec_static_cfg()
212 cfg->upper_start = STM32MP1_UPPER_OTP_START; in stm32mp_get_bsec_static_cfg()
213 cfg->max_id = STM32MP1_OTP_MAX_ID; in stm32mp_get_bsec_static_cfg()
/optee_os/lib/libmbedtls/core/
A Dsub.mk3 srcs-$(call cfg-one-enabled, CFG_CRYPTO_MD5 CFG_CRYPTO_SHA1 CFG_CRYPTO_SHA224 \
24 srcs-$(call cfg-one-enabled, CFG_CRYPTO_RSA CFG_CRYPTO_DH \
/optee_os/core/arch/arm/dts/
A Dstm32mp153.dtsi28 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
41 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
/optee_os/core/arch/arm/mm/
A Dcore_mmu_v7.c758 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
760 cfg->ttbr = core_mmu_get_main_ttb_pa(&default_partition) | in core_init_mmu_regs()
763 cfg->prrr = ATTR_DEVICE_PRRR | ATTR_NORMAL_CACHED_PRRR; in core_init_mmu_regs()
764 cfg->nmrr = ATTR_DEVICE_NMRR | ATTR_NORMAL_CACHED_NMRR; in core_init_mmu_regs()
766 cfg->prrr |= PRRR_NS1 | PRRR_DS1; in core_init_mmu_regs()
773 cfg->dacr = DACR_DOMAIN(0, DACR_DOMAIN_PERM_CLIENT) | in core_init_mmu_regs()
780 cfg->ttbcr = TTBCR_N_VALUE; in core_init_mmu_regs()
A Dcore_mmu_lpae.c820 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
825 cfg->ttbr0_base = virt_to_phys(base_xlation_table[0][0]); in core_init_mmu_regs()
826 cfg->ttbr0_core_offset = sizeof(base_xlation_table[0][0]); in core_init_mmu_regs()
830 cfg->mair0 = mair; in core_init_mmu_regs()
839 cfg->ttbcr = ttbcr; in core_init_mmu_regs()
880 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
886 cfg->ttbr0_el1_base = virt_to_phys(base_xlation_table[0][0]); in core_init_mmu_regs()
887 cfg->ttbr0_core_offset = sizeof(base_xlation_table[0][0]); in core_init_mmu_regs()
891 cfg->mair_el1 = mair; in core_init_mmu_regs()
907 cfg->tcr_el1 = tcr; in core_init_mmu_regs()
/optee_os/core/lib/libtomcrypt/src/ciphers/
A Dsub.mk1 subdirs-$(call cfg-one-enabled, _CFG_CORE_LTC_AES _CFG_CORE_LTC_AES_DESC) += aes
/optee_os/core/arch/arm/kernel/
A Dlink_dummies_init.c17 struct core_mmu_config *cfg __unused) in core_init_mmu_map()
/optee_os/core/pta/tests/
A Dsub.mk1 srcs-$(call cfg-all-enabled,CFG_REE_FS CFG_WITH_USER_TA) += fs_htree.c
/optee_os/core/drivers/crypto/se050/adaptors/utils/
A Dinfo.c136 static void show_config(uint16_t cfg) in show_config() argument
149 LOG_I("\t%s%s", cfg & features[i].val ? "with\t" : "without\t", in show_config()
/optee_os/core/tee/
A Dsub.mk45 ifeq ($(call cfg-one-enabled,CFG_WITH_USER_TA _CFG_WITH_SECURE_STORAGE),y)
/optee_os/core/drivers/crypto/se050/
A Dcrypto.mk51 se050-one-enabled = $(call cfg-one-enabled, \

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