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Searched refs:div (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/drivers/clk/sam/
A Dat91_pll.c40 uint8_t div; member
65 uint8_t div = 0; in clk_pll_enable() local
69 div = PLL_DIV(pllr); in clk_pll_enable()
74 (div == pll->div && mul == pll->mul)) in clk_pll_enable()
109 if (!pll->div || !pll->mul) in clk_pll_get_rate()
217 if (div) in clk_pll_get_best_div_mul()
218 *div = bestdiv; in clk_pll_get_best_div_mul()
232 uint32_t div = 1; in clk_pll_set_rate() local
237 &div, &mul, &index); in clk_pll_set_rate()
242 pll->div = div; in clk_pll_set_rate()
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A Dat91_peripheral.c25 uint32_t div; member
53 periph->div = shift; in clk_sam9x5_peripheral_autodiv()
68 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_enable()
104 periph->div = field_get(periph->layout->div_mask, status); in clk_sam9x5_peripheral_get_rate()
110 return parent_rate >> periph->div; in clk_sam9x5_peripheral_get_rate()
133 periph->div = shift; in clk_sam9x5_peripheral_set_rate()
171 periph->div = 0; in at91_clk_register_sam9x5_periph()
A Dat91_usb.c63 unsigned long div = 1; in at91sam9x5_clk_usb_set_rate() local
68 div = UDIV_ROUND_NEAREST(parent_rate, rate); in at91sam9x5_clk_usb_set_rate()
69 if (div > SAM9X5_USB_MAX_DIV + 1 || !div) in at91sam9x5_clk_usb_set_rate()
73 (div - 1) << SAM9X5_USB_DIV_SHIFT); in at91sam9x5_clk_usb_set_rate()
A Dat91_audio_pll.c46 #define AUDIO_PLL_QDPAD(qd, div) \ argument
49 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
67 uint8_t div; member
105 AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); in clk_audio_pll_pad_enable()
175 if (apad_ck->qdaudio && apad_ck->div) in clk_audio_pll_pad_get_rate()
176 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); in clk_audio_pll_pad_get_rate()
254 apad_ck->div = 3; in clk_audio_pll_pad_set_rate()
257 apad_ck->div = 2; in clk_audio_pll_pad_set_rate()
A Dat91_programmable.c98 unsigned long div = parent_rate / rate; in clk_programmable_set_rate() local
101 if (!div) in clk_programmable_set_rate()
105 shift = div - 1; in clk_programmable_set_rate()
110 shift = flsi(div) - 1; in clk_programmable_set_rate()
112 if (div != (1ULL << shift)) in clk_programmable_set_rate()
A Dat91_generated.c92 uint32_t div = 1; in clk_generated_set_rate() local
100 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_generated_set_rate()
101 if (div > GENERATED_MAX_DIV + 1 || !div) in clk_generated_set_rate()
104 gck->gckdiv = div - 1; in clk_generated_set_rate()
A Dat91_master.c26 uint8_t div; member
49 uint8_t div = 1; in clk_master_div_get_rate() local
60 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_get_rate()
62 rate /= charac->divisors[div]; in clk_master_div_get_rate()
/optee_os/core/drivers/
A Dimx_i2c.c172 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; in i2c_set_prescaler() local
174 if (div < p->divider) in i2c_set_prescaler()
176 else if (div > q->divider) in i2c_set_prescaler()
180 if (div <= p->divider) in i2c_set_prescaler()

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