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/optee_os/core/drivers/clk/
A D	clk-stm32mp15.c	719 uint32_t divy = 0; in stm32mp1_read_pll_freq() local 725 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; in stm32mp1_read_pll_freq() 727 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); in stm32mp1_read_pll_freq()

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