| /optee_os/core/arch/arm/plat-stm32mp1/drivers/ |
| A D | stm32mp1_syscfg.c | 64 io_clrbits32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); in stm32mp_syscfg_enable_io_compensation()
77 io_clrbits32(syscfg_base + SYSCFG_CMPCR, in stm32mp_syscfg_disable_io_compensation()
87 io_clrbits32(syscfg_base + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); in stm32mp_syscfg_disable_io_compensation()
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| A D | stm32mp1_pwr.c | 78 io_clrbits32(cr3, enable_mask); in stm32mp1_pwr_regulator_set_state()
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| A D | stm32mp1_rcc.c | 90 io_clrbits32(rcc_base + RCC_MP_GCR, RCC_MP_GCR_BOOT_MCU); in stm32_reset_assert_deassert_mcu()
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| /optee_os/core/arch/arm/plat-sunxi/ |
| A D | psci.c | 101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); in psci_cpu_on()
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| A D | main.c | 187 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK); in smc_init()
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| /optee_os/core/drivers/ |
| A D | bcm_sotp.c | 78 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
105 io_clrbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
120 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
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| A D | ls_gpio.c | 72 io_clrbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in gpio_set_value()
121 io_clrbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in gpio_set_direction()
170 io_clrbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
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| A D | zynqmp_csudma.c | 103 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
105 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
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| A D | bcm_gpio.c | 74 io_clrbits32(gc->base + offset, BIT(shift)); in iproc_clr_bit()
171 io_clrbits32(regaddr, BIT(shift)); in iproc_gpio_set_secure()
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| A D | stm32_i2c.c | 336 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in restore_cfg()
667 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in i2c_config_analog_filter()
670 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); in i2c_config_analog_filter()
781 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in stm32_i2c_init()
914 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_ack_failed()
1171 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_write()
1274 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in stm32_i2c_read_write_membyte()
1384 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_read()
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| A D | imx_mu.c | 38 io_clrbits32(base + MU_ACR_OFFSET, MU_CR_GIE_MASK | MU_CR_RIE_MASK | in mu_init()
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| A D | bcm_hwrng.c | 40 io_clrbits32(bcm_hwrng_base + in bcm_hwrng_reset()
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| A D | ls_dspi.c | 354 io_clrbits32(data->base + DSPI_MCR, DSPI_MCR_HALT); in ls_dspi_start()
409 io_clrbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs)); in dspi_set_cs_active_state()
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| A D | imx_rngb.c | 98 io_clrbits32(rng->base.va + RNG_CR, in irq_unmask()
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| A D | imx_ocotp.c | 95 io_clrbits32(g_base_addr + OCOTP_CTRL, OCOTP_CTRL_ERROR); in imx_ocotp_read()
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| A D | stm32_gpio.c | 437 io_clrbits32(base + GPIO_SECR_OFFSET, BIT(pin)); in stm32_gpio_set_secure_cfg()
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| A D | gic.c | 264 io_clrbits32(gd->gicd_base + GICD_IGROUPR(idx), mask); in gic_it_add()
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| /optee_os/core/drivers/clk/sam/ |
| A D | at91_audio_pll.c | 79 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
128 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
131 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
139 io_clrbits32(apad_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pad_disable()
147 io_clrbits32(apmc_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pmc_disable()
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| A D | at91_utmi.c | 92 io_clrbits32(utmi->pmc_base + AT91_CKGR_UCKR, AT91_PMC_UPLLEN); in clk_utmi_disable()
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| /optee_os/core/drivers/crypto/caam/hal/imx_8ulp/ |
| A D | hal_clk.c | 20 io_clrbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
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| /optee_os/core/arch/arm/plat-hisilicon/ |
| A D | psci.c | 88 io_clrbits32(crg + REG_CPU_SUSSYS_RESET, RELEASE_CORE_MASK); in psci_cpu_on()
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| /optee_os/core/arch/arm/plat-rzn1/ |
| A D | main.c | 102 io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); in rzn1_cm3_start()
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| /optee_os/core/include/ |
| A D | io.h | 133 static inline void io_clrbits32(vaddr_t addr, uint32_t clear_mask) in io_clrbits32() function
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| /optee_os/core/drivers/imx/dcp/ |
| A D | dcp.c | 83 io_clrbits32(ccm_base + CCM_CCGR0, DCP_CLK_ENABLE_MASK); in dcp_clk_enable()
155 io_clrbits32(dcp_base + DCP_STAT, BIT32(dcp_data->channel)); in dcp_run()
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| /optee_os/core/drivers/crypto/stm32/ |
| A D | stm32_cryp.c | 346 io_clrbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in cryp_end()
450 io_clrbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in save_context()
984 io_clrbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in stm32_cryp_update_load()
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