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Searched refs:io_clrsetbits32 (Results 1 – 19 of 19) sorted by relevance

/optee_os/core/drivers/
A Dstm32_gpio.c102 io_clrsetbits32(base + GPIO_MODER_OFFSET, in set_gpio_cfg()
107 io_clrsetbits32(base + GPIO_OTYPER_OFFSET, BIT(pin), cfg->otype << pin); in set_gpio_cfg()
110 io_clrsetbits32(base + GPIO_OSPEEDR_OFFSET, in set_gpio_cfg()
115 io_clrsetbits32(base + GPIO_PUPDR_OFFSET, BIT(pin), in set_gpio_cfg()
120 io_clrsetbits32(base + GPIO_AFRL_OFFSET, in set_gpio_cfg()
126 io_clrsetbits32(base + GPIO_AFRH_OFFSET, in set_gpio_cfg()
132 io_clrsetbits32(base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); in set_gpio_cfg()
A Dbcm_hwrng.c35 io_clrsetbits32(bcm_hwrng_base + RNG_CTRL_OFFSET, in bcm_hwrng_reset()
43 io_clrsetbits32(bcm_hwrng_base + RNG_CTRL_OFFSET, in bcm_hwrng_reset()
A Dmvebu_uart.c132 io_clrsetbits32(base + UART_BAUD_REG, 0x3FF, dll); in mvebu_uart_init()
A Dstm32_etzpc.c112 io_clrsetbits32(base + ETZPC_DECPROT0 + offset, in etzpc_configure_decprot()
A Dstm32_i2c.c986 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); in i2c_transfer_config()
/optee_os/core/drivers/clk/sam/
A Dat91_audio_pll.c83 io_clrsetbits32(frac->base + AT91_PMC_AUDIO_PLL1, in clk_audio_pll_frac_enable()
90 io_clrsetbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
103 io_clrsetbits32(apad_ck->base + AT91_PMC_AUDIO_PLL1, in clk_audio_pll_pad_enable()
106 io_clrsetbits32(apad_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pad_enable()
116 io_clrsetbits32(apmc_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pmc_enable()
A Dat91_main.c51 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_enable()
70 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_disable()
181 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in pmc_register_main_osc()
262 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in clk_sam9x5_main_set_parent()
A Dat91_utmi.c73 io_clrsetbits32(utmi->sfr_base + AT91_SFR_UTMICKTRIM, in clk_utmi_enable()
80 io_clrsetbits32(utmi->pmc_base + AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_enable()
A Dat91_usb.c45 io_clrsetbits32(usb->base + AT91_PMC_USB, usb->usbs_mask, index); in at91sam9x5_clk_usb_set_parent()
72 io_clrsetbits32(usb->base + AT91_PMC_USB, AT91_PMC_OHCIUSBDIV, in at91sam9x5_clk_usb_set_rate()
A Dat91_pll.c81 io_clrsetbits32(pll->base + AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), in clk_pll_enable()
85 io_clrsetbits32(pll->base + offset, layout->pllr_mask, in clk_pll_enable()
101 io_clrsetbits32(pll->base + PLL_REG(pll->id), mask, ~mask); in clk_pll_disable()
A Dat91_programmable.c65 io_clrsetbits32(prog->base + AT91_PMC_PCKR(prog->id), mask, pckr); in clk_programmable_set_parent()
119 io_clrsetbits32(prog->base + AT91_PMC_PCKR(prog->id), in clk_programmable_set_rate()
A Dat91_peripheral.c65 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_enable()
84 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_disable()
A Dat91_generated.c37 io_clrsetbits32(gck->base + gck->layout->offset, in clk_generated_enable()
55 io_clrsetbits32(gck->base + gck->layout->offset, AT91_PMC_PCR_GCKEN, in clk_generated_disable()
A Dat91_plldiv.c35 io_clrsetbits32(pmc->base + AT91_PMC_MCKR, AT91_PMC_PLLADIV2, in clk_plldiv_set_rate()
A Dat91_h32mx.c45 io_clrsetbits32(pmc->base + AT91_PMC_MCKR, AT91_PMC_H32MXDIV, mckr); in clk_sama5d4_h32mx_set_rate()
A Dat91_i2s_mux.c33 io_clrsetbits32(mux->sfr_base + AT91_SFR_I2SCLKSEL, in clk_i2s_mux_set_parent()
/optee_os/core/drivers/crypto/stm32/
A Dstm32_cryp.c421 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_ALGOMODE_MSK, in cryp_prepare_key()
434 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_ALGOMODE_MSK, in cryp_prepare_key()
583 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in do_from_init_to_phase()
615 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in do_from_header_to_phase()
1035 io_clrsetbits32(ctx->base + _CRYP_CR, in stm32_cryp_final()
1056 io_clrsetbits32(ctx->base + _CRYP_CR, _CRYP_CR_GCM_CCMPH_MSK, in stm32_cryp_final()
/optee_os/core/include/
A Dio.h138 static inline void io_clrsetbits32(vaddr_t addr, uint32_t clear_mask, in io_clrsetbits32() function
/optee_os/core/arch/arm/plat-stm32mp1/
A Dshared_resources.c62 io_clrsetbits32(va, clr, set); in io_clrsetbits32_stm32shregs()

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