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Searched refs:io_setbits32 (Results 1 – 25 of 37) sorted by relevance

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/optee_os/core/arch/arm/plat-stm32mp1/
A Drng_seed.c33 io_setbits32(rcc + RCC_MP_AHB5ENSETR, RCC_MP_AHB5ENSETR_RNG1EN); in plat_rng_init()
34 io_setbits32(rcc + RCC_MP_AHB5LPENCLRR, RCC_MP_AHB5LPENSETR_RNG1LPEN); in plat_rng_init()
35 io_setbits32(rcc + RCC_AHB5RSTSETR, RCC_AHB5RSTSETR_RNG1RST); in plat_rng_init()
39 io_setbits32(rcc + RCC_AHB5RSTCLRR, RCC_AHB5RSTSETR_RNG1RST); in plat_rng_init()
/optee_os/core/drivers/crypto/caam/hal/common/
A Dhal_jr.c41 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_reset()
142 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_disable_itr()
143 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_disable_itr()
164 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_check_ack_itr()
177 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_halt()
207 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_flush()
A Dhal_rng.c79 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_PRGM | TRNG_MCTL_ACC); in caam_hal_rng_kick()
146 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_ERR); in caam_hal_rng_kick()
/optee_os/core/drivers/
A Dbcm_sotp.c70 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
81 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
92 io_setbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
119 io_setbits32((bcm_sotp_base + SOTP_STATUS_1), SOTP_STATUS_1__CMD_DONE); in bcm_iproc_sotp_mem_read()
A Dls_gpio.c69 io_setbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in gpio_set_value()
119 io_setbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in gpio_set_direction()
168 io_setbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
232 io_setbits32(gpio_data->gpio_base + GPIOIBE, UINT32_MAX); in ls_gpio_init()
A Datmel_trng.c111 io_setbits32(trng_base + TRNG_CTRL, ctrl_val); in atmel_trng_reset()
113 io_setbits32(trng_base + TRNG_IER, 1); in atmel_trng_reset()
115 io_setbits32(trng_base + TRNG_CTRL, ctrl_val | 1); in atmel_trng_reset()
A Dimx_rngb.c90 io_setbits32(rng->base.va + RNG_CR, in irq_clear()
92 io_setbits32(rng->base.va + RNG_CMD, in irq_clear()
110 io_setbits32(rng->base.va + RNG_CR, RNG_CR_AR); in rng_seed()
A Dimx_ocotp.c34 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); in ocotp_clock_enable()
41 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), in ocotp_clock_enable()
49 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), in ocotp_clock_enable()
A Dzynqmp_csudma.c91 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
93 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
A Dstm32_i2c.c342 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); in restore_cfg()
674 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); in i2c_config_analog_filter()
677 io_setbits32(base + I2C_CR1, I2C_CR1_PE); in i2c_config_analog_filter()
801 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); in stm32_i2c_init()
807 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); in stm32_i2c_init()
827 io_setbits32(base + I2C_CR1, I2C_CR1_PE); in stm32_i2c_init()
855 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); in i2c_flush_txdr()
1492 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); in stm32_i2c_is_device_ready()
A Dbcm_hwrng.c38 io_setbits32(bcm_hwrng_base + in bcm_hwrng_reset()
A Dgic.c200 io_setbits32(gd->gicd_base + GICD_CTLR, GICD_CTLR_ENABLEGRP1S); in gic_init()
207 io_setbits32(gd->gicd_base + GICD_CTLR, in gic_init()
267 io_setbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask); in gic_it_add()
/optee_os/core/arch/arm/plat-rzn1/
A Dpsci.c78 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTEN, MEM_AREA_IO_SEC, in psci_system_reset()
83 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTCTRL, MEM_AREA_IO_SEC, in psci_system_reset()
A Dmain.c114 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); in rzn1_cm3_start()
115 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); in rzn1_cm3_start()
/optee_os/core/arch/arm/plat-sunxi/
A Dpsci.c127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); in psci_cpu_off()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_ctrl.c16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
A Dhal_clk.c18 io_setbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_ctrl.c15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_ctrl.c29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/arch/arm/plat-rockchip/
A Dplatform_px30.c48 io_setbits32(fw_base + FIREWALL_DDR_FW_DDR_CON_REG, BIT(rgn)); in platform_secure_ddr_region()
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_syscfg.c53 io_setbits32(syscfg_base + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); in stm32mp_syscfg_enable_io_compensation()
A Dstm32mp1_pwr.c69 io_setbits32(cr3, enable_mask); in stm32mp1_pwr_regulator_set_state()
A Dstm32mp1_rcc.c92 io_setbits32(rcc_base + RCC_MP_GCR, RCC_MP_GCR_BOOT_MCU); in stm32_reset_assert_deassert_mcu()
/optee_os/core/drivers/crypto/stm32/
A Dstm32_cryp.c427 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in cryp_prepare_key()
494 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_FFLUSH); in restore_context()
497 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in restore_context()
554 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in ccm_first_context()
587 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in do_from_init_to_phase()
964 io_setbits32(ctx->base + _CRYP_CR, _CRYP_CR_CRYPEN); in stm32_cryp_update_load()
/optee_os/core/arch/arm/plat-imx/drivers/
A Dimx_csu.c149 io_setbits32(csu_base + CSU_SA, csu_config->sa->lock_value); in csu_init()

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