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Searched refs:phys_to_virt (Results 1 – 25 of 62) sorted by relevance

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/optee_os/core/arch/arm/plat-sunxi/
A Dpsci.c72 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC, in psci_cpu_on()
74 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, in psci_cpu_on()
135 vaddr_t base = (vaddr_t)phys_to_virt(SUNXI_PRCM_BASE, MEM_AREA_IO_SEC, in psci_cpu_off()
137 vaddr_t cpucfg = (vaddr_t)phys_to_virt(SUNXI_CPUCFG_BASE, in psci_cpu_off()
A Dmain.c106 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC, in tzpc_init()
167 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC, in smc_base()
/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c105 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
150 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
152 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
185 va = (vaddr_t)phys_to_virt(SLCR_BASE, in write_slcr()
206 va = (vaddr_t)phys_to_virt(SLCR_BASE, in read_slcr()
/optee_os/core/drivers/
A Dhi16xx_rng.c42 vaddr_t alg = (vaddr_t)phys_to_virt(ALG_SC_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
44 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
79 r = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, 1) + in hw_get_random_byte()
A Ddra7_rng.c82 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in hw_get_random_byte()
129 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in dra7_rng_init()
/optee_os/core/arch/arm/plat-marvell/
A Dmain.c82 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
87 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
121 void *huk = phys_to_virt(PLAT_MARVELL_FUSF_FUSE_BASE + in tee_otp_get_hw_unique_key()
/optee_os/core/arch/arm/plat-vexpress/
A Dmain.c56 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
58 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
187 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); in init_tzc400()
211 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, in release_secondary_early_hpen()
/optee_os/core/arch/arm/plat-stm/
A Dmain.c93 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
141 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
142 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-sprd/
A Dmain.c56 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
58 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
/optee_os/core/arch/arm/plat-rockchip/
A Dmain.c33 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
38 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-k3/
A Dmain.c33 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, in main_init_gic()
35 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, in main_init_gic()
/optee_os/core/arch/arm/plat-mediatek/
A Dmain.c35 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
37 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
/optee_os/core/arch/arm/plat-uniphier/
A Dmain.c44 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
46 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
/optee_os/core/arch/arm/plat-imx/pm/
A Dpm-imx7.c102 iram_tbl_virt_addr = phys_to_virt(iram_tbl_phys_addr, in pm_imx7_iram_tbl_init()
111 map.va = (vaddr_t)phys_to_virt(phys_addr[i], MEM_AREA_IO_SEC, in pm_imx7_iram_tbl_init()
124 map.va = (vaddr_t)phys_to_virt(map.pa, MEM_AREA_TEE_COHERENT, in pm_imx7_iram_tbl_init()
133 map.va = (vaddr_t)phys_to_virt((paddr_t)GIC_BASE, MEM_AREA_IO_SEC, 1); in pm_imx7_iram_tbl_init()
/optee_os/core/arch/arm/plat-ti/
A Dmain.c44 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, in main_init_gic()
46 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, in main_init_gic()
98 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC, 1); in init_sec_mon()
/optee_os/core/arch/arm/kernel/
A Dtee_l2cc_mutex.c45 va = phys_to_virt(l2cc_mutex_pa, MEM_AREA_NSEC_SHM, MUTEX_SZ); in l2cc_mutex_alloc()
118 va = phys_to_virt(addr, MEM_AREA_NSEC_SHM, MUTEX_SZ); in tee_set_l2cc_mutex()
/optee_os/core/arch/arm/plat-zynqmp/
A Dmain.c84 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, in main_init_gic()
86 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, in main_init_gic()
/optee_os/core/pta/bcm/
A Delog.c97 src_vaddr = (vaddr_t)phys_to_virt((uintptr_t)src_paddr + offset, in pta_elog_load_nitro_fw()
166 src_vaddr = (vaddr_t)phys_to_virt((uintptr_t)src_paddr + offset, in pta_elog_nitro_crash_dump()
202 src_vaddr = (vaddr_t)phys_to_virt(src_paddr, MEM_AREA_RAM_NSEC, sz); in pta_elog_dump()
/optee_os/core/arch/arm/plat-rzn1/
A Dmain.c50 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
51 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); in main_init_gic()
/optee_os/core/arch/arm/plat-sam/
A Dmain.c65 va = phys_to_virt(SFR_BASE, MEM_AREA_IO_SEC, 1); in sam_sfr_base()
82 va = phys_to_virt(AT91C_BASE_MATRIX32, MEM_AREA_IO_SEC, in matrix32_base()
95 va = phys_to_virt(AT91C_BASE_MATRIX64, MEM_AREA_IO_SEC, in matrix64_base()
/optee_os/core/drivers/bnxt/
A Dbnxt_images.c101 phys_to_virt(QSPI_BNXT_IMG, MEM_AREA_IO_NSEC, in get_bnxt_images_info()
111 (vaddr_t)phys_to_virt(QSPI_BSPD_ADDR, in get_bnxt_images_info()
/optee_os/core/arch/arm/plat-ls/
A Dmain.c188 gicc_base = (vaddr_t)phys_to_virt(gic_base + gicc_offset, in main_init_gic()
190 gicd_base = (vaddr_t)phys_to_virt(gic_base + gicd_offset, in main_init_gic()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_clk.c14 vaddr_t pcc3_base = (vaddr_t)phys_to_virt(PCC3_BASE, MEM_AREA_IO_SEC, in caam_hal_clk_enable()
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_clk_mx7ulp.c14 vaddr_t pcc2_base = (vaddr_t)phys_to_virt(PCC2_BASE, MEM_AREA_IO_SEC, in caam_hal_clk_enable()
A Dhal_clk_mx7.c14 vaddr_t ccm_base = (vaddr_t)phys_to_virt(CCM_BASE, MEM_AREA_IO_SEC, 1); in caam_hal_clk_enable()

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