Searched refs:pll (Results 1 – 4 of 4) sorted by relevance
/optee_os/core/drivers/clk/sam/ |
A D | at91_pll.c | 74 (div == pll->div && mul == pll->mul)) in clk_pll_enable() 90 while (!clk_pll_ready(pll->base, pll->id)) in clk_pll_enable() 101 io_clrsetbits32(pll->base + PLL_REG(pll->id), mask, ~mask); in clk_pll_disable() 109 if (!pll->div || !pll->mul) in clk_pll_get_rate() 112 return (parent_rate / pll->div) * (pll->mul + 1); in clk_pll_get_rate() 242 pll->div = div; in clk_pll_set_rate() 243 pll->mul = mul; in clk_pll_set_rate() 276 pll = calloc(1, sizeof(*pll)); in at91_clk_register_pll() 277 if (!pll) { in at91_clk_register_pll() 282 pll->id = id; in at91_clk_register_pll() [all …]
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/optee_os/core/arch/arm/plat-rockchip/ |
A D | cru.h | 39 #define CRU_PLL_CON0(pll) ((pll) * 0x0c + 0x0) argument 40 #define CRU_PLL_CON1(pll) ((pll) * 0x0c + 0x4) argument 41 #define CRU_PLL_CON2(pll) ((pll) * 0x0c + 0x8) argument 47 #define PLL_MODE_BIT(pll) ((pll) * 4) argument 48 #define PLL_MODE_MSK(pll) BIT(PLL_MODE_BIT(pll)) argument 49 #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll)) argument 50 #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll)) argument
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A D | psci_rk322x.c | 85 static void pll_power_down(uint32_t pll) in pll_power_down() argument 89 io_write32(va_base + CRU_MODE_CON, PLL_SLOW_MODE(pll)); in pll_power_down() 90 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_DOWN); in pll_power_down() 93 static void pll_power_up(uint32_t pll) in pll_power_up() argument 97 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_UP); in pll_power_up() 100 static void pll_wait_lock(uint32_t pll) in pll_wait_lock() argument 105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock() 111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock() 112 EMSG("PLL can't lock, index = %" PRIu32, pll); in pll_wait_lock()
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/optee_os/core/drivers/clk/ |
A D | clk-stm32mp15.c | 664 return osc_frequency(pll->refclk[src]); in stm32mp1_pll_get_fref() 682 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); in stm32mp1_pll_get_fvco() 683 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); in stm32mp1_pll_get_fvco() 688 refclk = stm32mp1_pll_get_fref(pll); in stm32mp1_pll_get_fvco() 716 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq() local 724 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq() 727 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); in stm32mp1_read_pll_freq() 1076 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in get_parent_id_parent() local 1078 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & in get_parent_id_parent() 1081 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) in get_parent_id_parent() [all …]
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