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Searched refs:val (Results 1 – 25 of 176) sorted by relevance

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/optee_os/core/drivers/crypto/caam/hal/common/registers/
A Drng_regs.h28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16) argument
29 #define TRNG_SDCTL_SAMP_SIZE(val) ((val) & 0xFFFF) argument
42 #define TRNG_RTSCMISC_RTY_CNT(val) SHIFT_U32(((val) & (0xF)), 16) argument
44 #define TRNG_RTSCMISC_LRUN_MAX(val) SHIFT_U32(((val) & (0xFF)), 0) argument
49 #define TRNG_RTPKRRNG_PKR_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
54 #define TRNG_RTPKRMAX_PKR_MAX(val) SHIFT_U32(((val) & (0xFFFFFF)), 0) argument
59 #define TRNG_RTSCML_MONO_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 16) argument
61 #define TRNG_RTSCML_MONO_MAX(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
68 #define TRNG_RTSCR1L_RUN1_MAX(val) SHIFT_U32(((val) & (0x7FFF)), 0) argument
75 #define TRNG_RTSCR2L_RUN2_MAX(val) SHIFT_U32(((val) & (0x3FFF)), 0) argument
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A Dversion_regs.h15 #define GET_CTPR_MS_RNG_I(val) (((val) & BM_CTPR_MS_RNG_I) >> 8) argument
19 #define GET_CTPR_LS_SPLIT_KEY(val) (((val) & BM_CTPR_LS_SPLIT_KEY) >> 14) argument
24 #define GET_SMVID_MS_MAX_NPAG(val) (((val) & BM_SMVID_MS_MAX_NPAG) >> 16) argument
26 #define GET_SMVID_MS_NPRT(val) (((val) & BM_SMVID_MS_NPRT) >> 12) argument
30 #define GET_SMVID_LS_PSIZ(val) (((val) & BM_SMVID_LS_PSIZ) >> 16) argument
52 #define GET_CHANUM_LS_PKNUM(val) (((val) & BM_CHANUM_LS_PKNUM) >> 28) argument
54 #define GET_CHANUM_LS_MDNUM(val) (((val) & BM_CHANUM_LS_MDNUM) >> 12) argument
59 #define GET_PKHA_VERSION_PKNUM(val) ((val) & BM_PKHA_VERSION_PKNUM) argument
64 #define GET_MDHA_VERSION_MDNUM(val) ((val) & BM_MDHA_VERSION_MDNUM) argument
72 #define GET_RNG_VERSION_VID(val) ((val) & BM_RNG_VERSION_VID) argument
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/optee_os/core/drivers/crypto/caam/hal/common/
A Dhal_ctrl.c26 uint32_t val = 0; in caam_hal_ctrl_jrnum() local
42 uint32_t val = 0; in caam_hal_ctrl_hash_limit() local
83 uint32_t val = 0; in caam_hal_ctrl_pknum() local
101 uint32_t val = 0; in caam_hal_ctrl_inc_priblob() local
108 val &= PRIBLOB_MASK; in caam_hal_ctrl_inc_priblob()
111 if (val == 0 || val == 2) in caam_hal_ctrl_inc_priblob()
112 blob = val + 1; in caam_hal_ctrl_inc_priblob()
113 else if (val == 1) in caam_hal_ctrl_inc_priblob()
114 blob = val + 2; in caam_hal_ctrl_inc_priblob()
121 val |= blob; in caam_hal_ctrl_inc_priblob()
[all …]
A Dhal_rng.c67 uint32_t val = 0; in caam_hal_rng_kick() local
90 val = io_caam_read32(baseaddr + TRNG_SDCTL); in caam_hal_rng_kick()
91 val = GET_TRNG_SDCTL_ENT_DLY(val); in caam_hal_rng_kick()
93 if (ent_delay < val) { in caam_hal_rng_kick()
98 ent_delay = val; in caam_hal_rng_kick()
129 val = io_caam_read32(baseaddr + TRNG_MCTL); in caam_hal_rng_kick()
134 val &= ~BM_TRNG_MCTL_SAMP_MODE; in caam_hal_rng_kick()
135 val |= TRNG_MCTL_SAMP_MODE_RAW_ES_SC; in caam_hal_rng_kick()
137 val &= ~(TRNG_MCTL_PRGM | TRNG_MCTL_ACC); in caam_hal_rng_kick()
138 io_caam_write32(baseaddr + TRNG_MCTL, val); in caam_hal_rng_kick()
A Dhal_jr.c158 uint32_t val = 0; in caam_hal_jr_check_ack_itr() local
160 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_check_ack_itr()
162 if ((val & JRX_JRINTR_JRI) == JRX_JRINTR_JRI) { in caam_hal_jr_check_ack_itr()
174 uint32_t val = 0; in caam_hal_jr_halt() local
183 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_halt()
191 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_halt()
192 val &= BM_JRX_JRINTR_HALT; in caam_hal_jr_halt()
204 uint32_t val = 0; in caam_hal_jr_flush() local
213 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_flush()
221 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_flush()
[all …]
/optee_os/core/drivers/
A Dimx_snvs.c19 uint32_t val = 0; in snvs_get_security_cfg() local
21 val = io_read32(snvs + SNVS_HPSR); in snvs_get_security_cfg()
22 DMSG("HPSR: 0x%"PRIx32, val); in snvs_get_security_cfg()
23 if (val & SNVS_HPSR_SYS_SECURITY_BAD) in snvs_get_security_cfg()
27 else if (val & SNVS_HPSR_SYS_SECURITY_OPEN) in snvs_get_security_cfg()
29 else if (val > 4 && val < 8) in snvs_get_security_cfg()
39 uint32_t val = 0; in snvs_get_ssm_mode() local
41 val = io_read32(snvs + SNVS_HPSR); in snvs_get_ssm_mode()
42 val &= HPSR_SSM_ST_MASK; in snvs_get_ssm_mode()
43 val = val >> HPSR_SSM_ST_SHIFT; in snvs_get_ssm_mode()
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A Ddra7_rng.c79 uint32_t val[2]; in hw_get_random_byte() member
111 random.val[0] = io_read32(rng + RNG_OUTPUT_L); in hw_get_random_byte()
112 random.val[1] = io_read32(rng + RNG_OUTPUT_H); in hw_get_random_byte()
131 uint32_t val; in dra7_rng_init() local
147 val = 0; in dra7_rng_init()
150 val |= RNG_CONFIG_MIN_REFIL_CYCLES << in dra7_rng_init()
152 val |= RNG_CONFIG_MAX_REFIL_CYCLES << in dra7_rng_init()
154 io_write32(rng + RNG_CONFIG, val); in dra7_rng_init()
174 io_write32(rng + RNG_ALARMCNT, val); in dra7_rng_init()
178 val |= ENABLE_TRNG; in dra7_rng_init()
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A Dimx_ocotp.c82 if (!val) in imx_ocotp_read()
117 uint32_t val = 0; in ocotp_get_die_id_mx7ulp() local
120 res = imx_ocotp_read(2, 6, &val); in ocotp_get_die_id_mx7ulp()
123 uid = val & GENMASK_32(15, 0); in ocotp_get_die_id_mx7ulp()
125 res = imx_ocotp_read(2, 5, &val); in ocotp_get_die_id_mx7ulp()
130 res = imx_ocotp_read(2, 4, &val); in ocotp_get_die_id_mx7ulp()
135 res = imx_ocotp_read(2, 3, &val); in ocotp_get_die_id_mx7ulp()
150 uint32_t val = 0; in ocotp_get_die_id_mx() local
153 res = imx_ocotp_read(0, 2, &val); in ocotp_get_die_id_mx()
156 uid = val; in ocotp_get_die_id_mx()
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/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0) argument
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16) argument
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0) argument
/optee_os/core/include/
A Dio.h25 *(volatile uint8_t *)addr = val; in io_write8()
30 *(volatile uint16_t *)addr = val; in io_write16()
35 *(volatile uint32_t *)addr = val; in io_write32()
73 static inline void put_be64(void *p, uint64_t val) in put_be64() argument
75 *(uint64_t *)p = TEE_U64_TO_BIG_ENDIAN(val); in put_be64()
83 static inline void put_be32(void *p, uint32_t val) in put_be32() argument
85 *(uint32_t *)p = TEE_U32_TO_BIG_ENDIAN(val); in put_be32()
93 static inline void put_be16(void *p, uint16_t val) in put_be16() argument
95 *(uint16_t *)p = TEE_U16_TO_BIG_ENDIAN(val); in put_be16()
100 *(uint32_t *)p = val; in put_le32()
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/optee_os/core/lib/libfdt/
A Dfdt_addresses.c17 uint32_t val; in fdt_cells() local
27 val = fdt32_to_cpu(*c); in fdt_cells()
28 if (val > FDT_MAX_NCELLS) in fdt_cells()
31 return (int)val; in fdt_cells()
36 int val; in fdt_address_cells() local
39 if (val == 0) in fdt_address_cells()
41 if (val == -FDT_ERR_NOTFOUND) in fdt_address_cells()
43 return val; in fdt_address_cells()
48 int val; in fdt_size_cells() local
51 if (val == -FDT_ERR_NOTFOUND) in fdt_size_cells()
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/optee_os/core/arch/arm/plat-imx/pm/
A Dpsci.c58 uint32_t val; in psci_cpu_on() local
70 val = virt_to_phys((void *)TEE_TEXT_VA_START); in psci_cpu_on()
78 val = io_read32(va + SRC_A7RCR1); in psci_cpu_on()
81 io_write32(va + SRC_A7RCR1, val); in psci_cpu_on()
87 val = io_read32(va + SRC_SCR); in psci_cpu_on()
90 io_write32(va + SRC_SCR, val); in psci_cpu_on()
123 uint32_t cpu, val; in psci_affinity_info() local
145 val = io_read32(va + SRC_A7RCR1); in psci_affinity_info()
147 io_write32(va + SRC_A7RCR1, val); in psci_affinity_info()
153 val = io_read32(va + SRC_SCR); in psci_affinity_info()
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A Dgpcv2.c21 uint32_t val = io_read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc() local
24 val |= GPC_PGC_PCG_MASK; in imx_gpcv2_set_core_pgc()
26 io_write32(gpc_base() + offset, val); in imx_gpcv2_set_core_pgc()
31 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ); in imx_gpcv2_set_core1_pdn_by_software() local
35 val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK; in imx_gpcv2_set_core1_pdn_by_software()
37 io_write32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ, val); in imx_gpcv2_set_core1_pdn_by_software()
48 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ); in imx_gpcv2_set_core1_pup_by_software() local
52 val |= GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK; in imx_gpcv2_set_core1_pup_by_software()
54 io_write32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ, val); in imx_gpcv2_set_core1_pup_by_software()
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
/optee_os/core/lib/libfdt/include/
A Dlibfdt.h251 fdth->name = cpu_to_fdt32(val); \
1253 const void *val, int len);
1287 fdt32_t tmp = cpu_to_fdt32(val); in fdt_setprop_inplace_u32()
1322 fdt64_t tmp = cpu_to_fdt64(val); in fdt_setprop_inplace_u64()
1437 fdt32_t tmp = cpu_to_fdt32(val); in fdt_property_u32()
1442 fdt64_t tmp = cpu_to_fdt64(val); in fdt_property_u64()
1584 const void *val, int len);
1646 uint32_t val) in fdt_setprop_u32() argument
1681 uint64_t val) in fdt_setprop_u64() argument
1693 uint32_t val) in fdt_setprop_cell() argument
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/optee_os/core/drivers/crypto/se050/core/
A Dstorage.c15 uint32_t val = SE050_KEY_WATERMARK; in crypto_storage_obj_del() local
24 if (memcmp(p, &val, sizeof(val)) != 0) { in crypto_storage_obj_del()
36 memcpy((void *)&val, p, sizeof(val)); in crypto_storage_obj_del()
38 if (val < OID_MIN || val > OID_MAX) in crypto_storage_obj_del()
45 status = sss_se05x_key_object_get_handle(&k_object, val); in crypto_storage_obj_del()
/optee_os/core/arch/arm/include/
A Darm32.h241 uint32_t val; in read_pc() local
243 asm volatile ("adr %0, ." : "=r" (val)); in read_pc()
244 return val; in read_pc()
249 uint32_t val; in read_sp() local
252 return val; in read_sp()
257 uint32_t val; in read_lr() local
260 return val; in read_lr()
265 uint32_t val; in read_fp() local
268 return val; in read_fp()
273 uint32_t val; in read_r7() local
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/optee_os/out/arm/export-ta_arm32/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int() argument
48 __compiler_atomic_store(p, val); in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short() argument
53 __compiler_atomic_store(p, val); in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint() argument
58 __compiler_atomic_store(p, val); in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32() argument
63 __compiler_atomic_store(p, val); in atomic_store_u32()
/optee_os/out/arm/export-ta_arm64/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int() argument
48 __compiler_atomic_store(p, val); in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short() argument
53 __compiler_atomic_store(p, val); in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint() argument
58 __compiler_atomic_store(p, val); in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32() argument
63 __compiler_atomic_store(p, val); in atomic_store_u32()
/optee_os/lib/libutils/ext/include/
A Datomic.h46 static inline void atomic_store_int(int *p, int val) in atomic_store_int() argument
48 __compiler_atomic_store(p, val); in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short() argument
53 __compiler_atomic_store(p, val); in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint() argument
58 __compiler_atomic_store(p, val); in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32() argument
63 __compiler_atomic_store(p, val); in atomic_store_u32()
/optee_os/core/arch/arm/plat-imx/
A Dimx_pl310.c29 uint32_t val = 0; in arm_cl2_config() local
50 val = PL310_PREFETCH_CTRL_INIT; in arm_cl2_config()
56 val &= ~PL310_PREFETCH_DOUBLE_LINEFILL; in arm_cl2_config()
58 io_write32(pl310_base + PL310_PREFETCH_CTRL, val); in arm_cl2_config()
68 uint32_t val __maybe_unused; in arm_cl2_enable()
75 val = io_read32(pl310_base + PL310_AUX_CTRL); in arm_cl2_enable()
76 if (val & PL310_AUX_CTRL_FLZW) in arm_cl2_enable()
113 uint32_t val = PL310_DEBUG_CTRL_DISABLE_WRITEBACK | in pl310_disable_writeback() local
116 io_write32(base + PL310_DEBUG_CTRL, val); in pl310_disable_writeback()
/optee_os/core/arch/arm/plat-marvell/armada3700/
A Dhal_sec_perf.c70 #define TZ_SET_PERM(data, val) \ argument
73 (data) |= (((val) & 0x3) << 1); \
77 #define TZ_SET_RZ_EN(data, val) \ argument
80 (data) |= (((val) & 0x1) << 3); \
88 (data) |= (((val) & 0x1F) << 8); \
97 (data) |= (((val) & 0xFFF00000)); \
101 #define TZ_SET_UR_PERM(data, val) \ argument
104 (data) |= (((val) & 0x3) << 4); \
107 #define TZ_GET_UR_RZ_EN(data, val) \ argument
110 #define TZ_SET_UR_RZ_EN(data, val) \ argument
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/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_jr.c27 uint32_t val = 0; in caam_hal_jr_setowner() local
33 val = io_caam_read32(ctrl_base + JRxMIDR_MS(jr_idx)); in caam_hal_jr_setowner()
34 HAL_TRACE("JR%" PRIu32 "MIDR_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
53 if (val & JRxMIDR_MS_LMID) { in caam_hal_jr_setowner()
60 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
61 if ((cfg_ms | JRxMIDR_MS_LMID) == val) { in caam_hal_jr_setowner()
66 val = io_caam_read32(ctrl_base + JRxMIDR_LS(jr_idx)); in caam_hal_jr_setowner()
69 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
70 if (val == cfg_ls) in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_jr.c27 uint32_t val = 0; in caam_hal_jr_setowner() local
33 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
34 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
52 if (val & JRxDID_MS_LDID) { in caam_hal_jr_setowner()
59 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
60 if ((cfg_ms | JRxDID_MS_LDID) == val) { in caam_hal_jr_setowner()
62 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
65 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
66 if (val == cfg_ls) in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_jr.c28 uint32_t val = 0; in caam_hal_jr_setowner() local
34 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
35 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
53 if (val & JRxDID_MS_LDID) { in caam_hal_jr_setowner()
60 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
61 if ((cfg_ms | JRxDID_MS_LDID) == val) { in caam_hal_jr_setowner()
63 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
66 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
67 if (val == cfg_ls) in caam_hal_jr_setowner()

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