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Searched refs:APB_SLAVE_SECURITY_ENABLE (Results 1 – 3 of 3) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_setup.c246 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in plat_late_platform_setup()
248 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in plat_late_platform_setup()
253 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in plat_late_platform_setup()
255 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in plat_late_platform_setup()
A Dplat_psci_handlers.c399 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in tegra_soc_pwr_domain_power_down_wfi()
401 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in tegra_soc_pwr_domain_power_down_wfi()
498 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in tegra_soc_pwr_domain_on_finish()
500 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in tegra_soc_pwr_domain_on_finish()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/
A Dtegra_def.h192 #define APB_SLAVE_SECURITY_ENABLE U(0xC00) macro

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