| /tf-a-ffa_el3_spmc/plat/mediatek/common/ |
| A D | mtk_cirq.c | 77 mask->mask1 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
79 mask->mask2 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
81 mask->mask3 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
83 mask->mask4 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
85 mask->mask5 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
87 mask->mask6 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
89 mask->mask7 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
91 mask->mask8 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
93 mask->mask9 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
95 mask->mask10 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
[all …]
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/ |
| A D | fvp_def.h | 60 #define DEVICE1_BASE BASE_GICD_BASE
64 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
68 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
137 #define BASE_GICD_BASE UL(0x2f000000) macro
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| A D | fvp_common.c | 52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
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| /tf-a-ffa_el3_spmc/plat/qti/sc7180/inc/ |
| A D | platform_def.h | 130 #define BASE_GICD_BASE 0x17A00000 macro
136 #define QTI_GICD_BASE BASE_GICD_BASE
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/include/ |
| A D | plat_macros.S | 23 mov_imm x16, BASE_GICD_BASE
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| A D | platform_def.h | 109 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| A D | zynqmp_def.h | 114 #define BASE_GICD_BASE 0xF9010000 macro
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/ |
| A D | plat_mt_gic.c | 26 BASE_GICD_BASE, in plat_mt_gic_init()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | plat_mt_gic.c | 19 .gicd_base = BASE_GICD_BASE,
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/ |
| A D | rk3399_def.h | 29 #define BASE_GICD_BASE (GIC500_BASE) macro
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/include/ |
| A D | plat_macros.S | 33 mov_imm x16, BASE_GICD_BASE
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| A D | platform_def.h | 284 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/ |
| A D | platform_def.h | 89 #define PLAT_RK_GICD_BASE BASE_GICD_BASE
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| /tf-a-ffa_el3_spmc/plat/mediatek/common/drivers/gic600/ |
| A D | mt_gic_v3.c | 183 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
194 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8183/include/ |
| A D | plat_macros.S | 35 mov_imm x26, BASE_GICD_BASE
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| A D | platform_def.h | 116 #define BASE_GICD_BASE MT_GIC_BASE macro
130 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/include/ |
| A D | plat_macros.S | 29 mov_imm x16, BASE_GICD_BASE
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| A D | platform_def.h | 58 #define BASE_GICD_BASE (MT_GIC_BASE+0x1000) macro
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/include/ |
| A D | plat_macros.S | 35 mov_imm x16, BASE_GICD_BASE
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| A D | platform_def.h | 118 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| A D | mt8173_def.h | 68 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) macro
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8195/include/ |
| A D | platform_def.h | 77 #define BASE_GICD_BASE MT_GIC_BASE macro
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8192/include/ |
| A D | platform_def.h | 82 #define BASE_GICD_BASE MT_GIC_BASE macro
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/ |
| A D | pm_client.c | 180 uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4; in pm_client_set_wakeup_sources()
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| A D | pm_svc_main.c | 154 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, in zynqmp_sgi7_irq()
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