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Searched refs:BIT_32 (Results 1 – 20 of 20) sorted by relevance

/tf-a-ffa_el3_spmc/include/drivers/arm/fvp/
A Dfvp_pwrc.h17 #define PWKUPR_WEN BIT_32(31)
19 #define PSYSR_AFF_L2 BIT_32(31)
20 #define PSYSR_AFF_L1 BIT_32(30)
21 #define PSYSR_AFF_L0 BIT_32(29)
22 #define PSYSR_WEN BIT_32(28)
23 #define PSYSR_PC BIT_32(27)
24 #define PSYSR_PP BIT_32(26)
/tf-a-ffa_el3_spmc/include/drivers/arm/
A Dgicv2.h71 #define EOI_MODE_NS BIT_32(10)
72 #define EOI_MODE_S BIT_32(9)
73 #define IRQ_BYP_DIS_GRP1 BIT_32(8)
74 #define FIQ_BYP_DIS_GRP1 BIT_32(7)
75 #define IRQ_BYP_DIS_GRP0 BIT_32(6)
76 #define FIQ_BYP_DIS_GRP0 BIT_32(5)
77 #define CBPR BIT_32(4)
79 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
80 #define ACK_CTL BIT_32(2)
114 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
A Dgicv3.h130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
199 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
208 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
209 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
237 #define ICC_SRE_EN_BIT BIT_32(3)
238 #define ICC_SRE_DIB_BIT BIT_32(2)
239 #define ICC_SRE_DFB_BIT BIT_32(1)
240 #define ICC_SRE_SRE_BIT BIT_32(0)
302 #define GITS_CTLR_ENABLED_BIT BIT_32(0)
[all …]
A Dcci.h70 #define DVM_EN_BIT BIT_32(1)
71 #define SNOOP_EN_BIT BIT_32(0)
72 #define SUPPORT_SNOOPS BIT_32(30)
73 #define SUPPORT_DVM BIT_32(31)
76 #define CHANGE_PENDING_BIT BIT_32(0)
A Dtzc380.h45 #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
46 #define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
60 #define TZC_SP_NS_W BIT_32(0)
61 #define TZC_SP_NS_R BIT_32(1)
62 #define TZC_SP_S_W BIT_32(2)
63 #define TZC_SP_S_R BIT_32(3)
A Dtzc400.h47 #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
48 #define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
A Dgic_common.h62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
/tf-a-ffa_el3_spmc/include/plat/arm/board/common/
A Dv2m_def.h23 #define V2M_CFGCTRL_START BIT_32(31)
24 #define V2M_CFGCTRL_RW BIT_32(30)
96 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
97 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
98 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
99 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
/tf-a-ffa_el3_spmc/services/std_svc/sdei/
A Dsdei_private.h100 return ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U); in is_event_private()
110 return ((map->map_flags & BIT_32(SDEI_MAPF_CRITICAL_SHIFT_)) != 0U); in is_event_critical()
120 return ((map->map_flags & BIT_32(SDEI_MAPF_SIGNALABLE_SHIFT_)) != 0U); in is_event_signalable()
125 return ((map->map_flags & BIT_32(SDEI_MAPF_DYNAMIC_SHIFT_)) != 0U); in is_map_dynamic()
136 return ((map->map_flags & BIT_32(SDEI_MAPF_BOUND_SHIFT_)) != 0U); in is_map_bound()
141 map->map_flags |= BIT_32(SDEI_MAPF_BOUND_SHIFT_); in set_map_bound()
146 return ((map->map_flags & BIT_32(SDEI_MAPF_EXPLICIT_SHIFT_)) != 0U); in is_map_explicit()
151 map->map_flags &= ~BIT_32(SDEI_MAPF_BOUND_SHIFT_); in clr_map_bound()
181 return ((se->state & BIT_32(bit_no)) != 0U); in get_ev_state_bit()
186 se->state &= ~BIT_32(bit_no); in clr_ev_state_bit()
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_a64/
A Dsunxi_power.c46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
53 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
62 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
238 code[0] = (code[0] & ~0xffff) | BIT_32(core); in sunxi_cpu_power_off_self()
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/
A Dfvp_def.h122 #define FVP_SP810_CTRL_TIM0_OV BIT_32(16)
123 #define FVP_SP810_CTRL_TIM1_OV BIT_32(18)
124 #define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
125 #define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
/tf-a-ffa_el3_spmc/drivers/arm/gic/v3/
A Dgic600_multichip_private.h22 #define GICD_DCHIPR_PUP_BIT BIT_32(0)
23 #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5))
A Dgicv3_main.c1117 tgt = BIT_32(aff0); in gicv3_raise_secure_g0_sgi()
/tf-a-ffa_el3_spmc/drivers/arm/tzc/
A Dtzc400.c76 mmio_write_32(base + INT_CLEAR, BIT_32(filter)); in _tzc400_clear_it()
81 return mmio_read_32(base + INT_STATUS) & BIT_32(filter); in _tzc400_get_int_by_filter()
122 if (((control_fail & BIT_32(FAIL_CONTROL_NS_SHIFT)) >> FAIL_CONTROL_NS_SHIFT) == in _tzc400_dump_fail_filter()
129 if (((control_fail & BIT_32(FAIL_CONTROL_PRIV_SHIFT)) >> FAIL_CONTROL_PRIV_SHIFT) == in _tzc400_dump_fail_filter()
136 if (((control_fail & BIT_32(FAIL_CONTROL_DIR_SHIFT)) >> FAIL_CONTROL_DIR_SHIFT) == in _tzc400_dump_fail_filter()
/tf-a-ffa_el3_spmc/drivers/scmi-msg/
A Dsmt.c47 #define SMT_STATUS_FREE BIT_32(0)
49 #define SMT_STATUS_ERROR BIT_32(1)
52 #define SMT_FLAG_INTR_ENABLED BIT_32(1)
/tf-a-ffa_el3_spmc/include/lib/
A Dutils_def.h22 #define BIT_32(nr) (U(1) << (nr)) macro
28 #define BIT BIT_32
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h6/
A Dsunxi_power.c118 mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core)); in sunxi_cpu_power_off_self()
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h616/
A Dsunxi_power.c120 mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core)); in sunxi_cpu_power_off_self()
/tf-a-ffa_el3_spmc/drivers/mmc/
A Dmmc.c303 mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len); in mmc_fill_device_info()
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A Darch.h313 #define SPSR_SSBS_BIT BIT_32(23)

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