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Searched refs:CPG_PLL4CR (Results 1 – 3 of 3) sorted by relevance

/tf-a-ffa_el3_spmc/plat/renesas/common/include/
A Drcar_def.h226 #define CPG_PLL4CR (CPG_BASE + 0x01F4U) macro
/tf-a-ffa_el3_spmc/plat/renesas/rzg/
A Dbl2_plat_setup.c931 reg = mmio_read_32(CPG_PLL4CR); in bl2_el3_early_platform_setup()
933 mmio_write_32(CPG_PLL4CR, reg); in bl2_el3_early_platform_setup()
/tf-a-ffa_el3_spmc/plat/renesas/rcar/
A Dbl2_plat_setup.c1084 reg = mmio_read_32(CPG_PLL4CR); in bl2_el3_early_platform_setup()
1086 mmio_write_32(CPG_PLL4CR, reg); in bl2_el3_early_platform_setup()

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