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Searched refs:CRU_BASE (Results 1 – 21 of 21) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/
A Dsoc.c43 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
147 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in plls_resume()
149 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in plls_resume()
151 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in plls_resume()
153 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in plls_resume()
155 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), in plls_resume()
179 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in pm_plls_resume()
181 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in pm_plls_resume()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/pmu/
A Dpmu.c336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
383 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_suspend()
387 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_suspend()
391 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_suspend()
395 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_suspend()
399 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), in pm_plls_suspend()
403 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_suspend()
411 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_resume()
429 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_resume()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/
A Dsoc.c47 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
133 mmio_write_32(CRU_BASE + PLL_MODE_CON, 0xf3030000); in clk_plls_suspend()
139 mmio_write_32(CRU_BASE + PLL_MODE_CON, in clk_plls_resume()
149 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
165 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
175 mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(i)); in clk_sel_con_save()
191 mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(i), val); in clk_sel_con_restore()
209 mmio_write_32(CRU_BASE + PLL_MODE_CON, 0xf3030000); in rockchip_soc_soft_reset()
211 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in rockchip_soc_soft_reset()
214 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/src/
A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); in ddr_set_pll()
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, in ddr_set_pll()
48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, in ddr_set_pll()
50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/soc/
A Dsoc.c58 mmio_write_32((CRU_BASE + in set_pll_slow_mode()
67 mmio_write_32(CRU_BASE + in set_pll_normal_mode()
77 mmio_write_32(CRU_BASE + in set_pll_bypass()
130 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
138 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in restore_pll()
159 dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); in save_pll()
191 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); in clk_gate_con_save()
202 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
214 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), in clk_gate_con_restore()
224 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in set_plls_nobypass()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.c52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
78 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_disable()
91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()
93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()
109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()
111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in px30_soc_reset_config()
113 tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH); in px30_soc_reset_config()
116 mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp); in px30_soc_reset_config()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/gpio/
A Drk3399_gpio.c93 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
96 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
101 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
104 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
109 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
112 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
140 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
145 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
151 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/secure/
A Dsecure.c147 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in secure_sgrf_init()
150 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in secure_sgrf_init()
156 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in secure_sgrf_init()
158 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in secure_sgrf_init()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/
A Drk3368_def.h22 #define CRU_BASE 0xff760000 macro
53 #define CRU_BASE 0xff760000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/
A Dsuspend.c131 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), in rkclk_ddr_reset()
486 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()
655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
657 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
658 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
659 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
665 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
673 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 1 << 1); in pmusram_enable_watchdog()
708 cru_clksel_con6 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON6); in dmc_suspend()
710 dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i)); in dmc_suspend()
[all …]
A Ddfs.c1716 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; in ddr_get_rate()
1717 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; in ddr_get_rate()
1719 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; in ddr_get_rate()
1721 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; in ddr_get_rate()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.c390 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
394 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
397 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); in ddr_reg_save()
400 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
404 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
407 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
410 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
419 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); in ddr_reg_save()
424 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13); in ddr_reg_save()
425 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13)) in ddr_reg_save()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/pmu/
A Dpmu.c528 mmio_write_32(CRU_BASE + (con), ((msk) << 16) | 0xffff)
550 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_suspend()
551 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_suspend()
572 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_resume()
887 mmio_write_32(CRU_BASE + CRU_MODE, val); in pll_set_mode()
899 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
917 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_resume()
943 mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0), in pm_plls_suspend()
947 mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0), in pm_plls_suspend()
954 mmio_write_32(CRU_BASE + CRU_CLKSELS_CON(0), in pm_plls_resume()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c40 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
146 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); in sgrf_init()
148 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); in sgrf_init()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/pmu/
A Dplat_pmu_macros.S53 ldr x7, =(CRU_BASE + 0xc)
110 mov x5, CRU_BASE
A Dpmu.c586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
619 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
933 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1053 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1283 store_cru[i / 4] = mmio_read_32(CRU_BASE + i); in cru_register_save()
1306 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
1312 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
1314 mmio_write_32(CRU_BASE + i, in cru_register_restore()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/pmu/
A Dpmu.c217 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_on()
226 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), BIT(cpu_id) << 16); in cpus_power_domain_on()
242 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_off()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/
A Drk3288_def.h60 #define CRU_BASE 0xff760000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/
A Drk3328_def.h33 #define CRU_BASE 0xff440000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/px30/
A Dpx30_def.h94 #define CRU_BASE 0xff2b0000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/shared/
A Daddressmap_shared.h38 #define CRU_BASE (MMIO_BASE + 0x07760000) macro

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