Searched refs:CRU_CLKGATE_CON (Results 1 – 8 of 8) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/gpio/ |
| A D | rk3399_gpio.c | 94 CRU_CLKGATE_CON(31)) >> in gpio_get_clock()
96 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
102 CRU_CLKGATE_CON(31)) >> in gpio_get_clock()
104 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
110 CRU_CLKGATE_CON(31)) >> in gpio_get_clock()
112 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
140 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
145 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
151 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
[all …]
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/pmu/ |
| A D | pmu.c | 255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
517 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in ddr_suspend()
519 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in ddr_suspend()
521 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in ddr_suspend()
523 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in ddr_suspend()
534 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in dmc_restore()
536 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in dmc_restore()
538 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in dmc_restore()
[all …]
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| /tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/ |
| A D | soc.h | 63 #define CRU_CLKGATE_CON 0x200 macro
64 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4)
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.h | 45 #define CRU_CLKGATE_CON 0x160 macro
46 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.h | 83 #define CRU_CLKGATE_CON 0x200 macro
84 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.h | 42 #define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4)) macro
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/soc/ |
| A D | soc.h | 190 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) macro
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/pmu/ |
| A D | pmu.c | 843 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); in sys_slp_config()
844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
929 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> in suspend_apio()
933 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1053 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1446 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), in rockchip_soc_sys_pwr_dm_resume()
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